產品詳細資料

Technology family LV-A Number of channels 6 IOL (max) (mA) 12 IOH (max) (mA) -12 Supply current (max) (µA) 20 Input type Schmitt-Trigger Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
Technology family LV-A Number of channels 6 IOL (max) (mA) 12 IOH (max) (mA) -12 Supply current (max) (µA) 20 Input type Schmitt-Trigger Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
TSSOP (PW) 14 32 mm² (5 mm × 6.4 mm)
  • 2 V to 5.5 V V CC operation
  • Maximum t pd of 14 ns at 5 V
  • Supports mixed-mode voltage operation on all ports
  • I off supports partial-power-down mode operation
  • Latch-up performance exceeds 250 mA per JESD 17
  • Operating ambient temperature: -55°C to +125°C
  • Supports defense, aerospace, and medical applications:
    • Controlled baseline
    • One assembly and test site
    • One fabrication site
    • Extended product life cycle
    • Product traceability
  • 2 V to 5.5 V V CC operation
  • Maximum t pd of 14 ns at 5 V
  • Supports mixed-mode voltage operation on all ports
  • I off supports partial-power-down mode operation
  • Latch-up performance exceeds 250 mA per JESD 17
  • Operating ambient temperature: -55°C to +125°C
  • Supports defense, aerospace, and medical applications:
    • Controlled baseline
    • One assembly and test site
    • One fabrication site
    • Extended product life cycle
    • Product traceability

The SN74LV14B-EP device contains six independent Inverter with Schmitt-trigger inputs designed for 2 V to 5.5 V V CC operation. Each gate performs the Boolean function Y = A in positive logic.

This device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

The SN74LV14B-EP device contains six independent Inverter with Schmitt-trigger inputs designed for 2 V to 5.5 V V CC operation. Each gate performs the Boolean function Y = A in positive logic.

This device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

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* 資料表 SN74LV14B-EP Enhanced Product, 2-V to 5.5-V, Low-Noise, HexSchmitt-Trigger Inverters datasheet PDF | HTML 2023/8/24

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14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組

14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。

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