SN74LV132A

現行

產品詳細資料

Technology family LV-A Number of channels 4 Inputs per channel 4 IOL (max) (mA) 12 IOH (max) (mA) -12 Input type Schmitt-Trigger Output type Push-Pull Features High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff) Data rate (max) (Mbps) 70 Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LV-A Number of channels 4 Inputs per channel 4 IOL (max) (mA) 12 IOH (max) (mA) -12 Input type Schmitt-Trigger Output type Push-Pull Features High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff) Data rate (max) (Mbps) 70 Rating Catalog Operating temperature range (°C) -40 to 125
TVSOP (DGV) 14 23.04 mm² (3.6 mm × 6.4 mm) SOIC (D) 14 51.9 mm² (8.65 mm × 6 mm) TSSOP (PW) 14 32 mm² (5 mm × 6.4 mm) SOP (NS) 14 79.56 mm² (10.2 mm × 7.8 mm) SSOP (DB) 14 48.36 mm² (6.2 mm × 7.8 mm)
  • 2-V to 5.5-V VCC Operation
  • Max tpd of 9 ns at 5 V
  • Typical VOLP (Output Ground Bounce) <0.8 V at
    VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2.3 V at
    VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on All
    Ports
  • Latch-Up Performance Exceeds 250 mA per
    JESD 17
  • Ioff Supports Live Insertion, Partial Power-Down
    Mode, and Back Drive Protection
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • APPLICATIONS
    • Industrial PC: Rugged PC and Laptop
    • Access Control and Security: Camera
      Surveillance IP Network
    • Vending, Payment and Change Machines
    • Patient Monitoring STB / DVR / Streaming Media
      (Withdraw)
    • Other Motor Drives (Such as Switch Reluctance)

All other trademarks are the property of their respective owners

  • 2-V to 5.5-V VCC Operation
  • Max tpd of 9 ns at 5 V
  • Typical VOLP (Output Ground Bounce) <0.8 V at
    VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2.3 V at
    VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on All
    Ports
  • Latch-Up Performance Exceeds 250 mA per
    JESD 17
  • Ioff Supports Live Insertion, Partial Power-Down
    Mode, and Back Drive Protection
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • APPLICATIONS
    • Industrial PC: Rugged PC and Laptop
    • Access Control and Security: Camera
      Surveillance IP Network
    • Vending, Payment and Change Machines
    • Patient Monitoring STB / DVR / Streaming Media
      (Withdraw)
    • Other Motor Drives (Such as Switch Reluctance)

All other trademarks are the property of their respective owners

The ’LV132A devices are quadruple positive-NAND gates designed for 2-V to 5.5-V VCC operation.

The ’LV132A devices perform the Boolean function Y = A • B or Y = A + B in positive logic.

Each circuit functions as a NAND gate, but because of the Schmitt trigger, it has different input threshold levels for positive- and negative-going signals.

These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give clean jitter-free output signals.

The ’LV132A devices are quadruple positive-NAND gates designed for 2-V to 5.5-V VCC operation.

The ’LV132A devices perform the Boolean function Y = A • B or Y = A + B in positive logic.

Each circuit functions as a NAND gate, but because of the Schmitt trigger, it has different input threshold levels for positive- and negative-going signals.

These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give clean jitter-free output signals.

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 SNx4LV132A Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs datasheet (Rev. J) PDF | HTML 2015/2/20

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開發板

14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組

14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。

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模擬型號

HSPICE Model for SN74LV132A

SCEJ153.ZIP (51 KB) - HSpice 模型
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模擬型號

SN74LV132A Behavioral SPICE Model

SCLM188.ZIP (7 KB) - PSpice 模型
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模擬型號

SN74LV132A IBIS Model (Rev. A)

SCEM128 (114 KB) - IBIS 模型
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
TVSOP (DGV) 14 Ultra Librarian
SOIC (D) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian
SOP (NS) 14 Ultra Librarian
SSOP (DB) 14 Ultra Librarian

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