SN74LV126A
- 2V to 5.5V VCC operation
- Maximum tpd of 6.5ns at 5V
- Typical VOLP (output ground bounce) <0.8V at VCC = 3.3V, TA = 25°C
- Typical VOHV (output VOH undershoot) >2.3V at VCC = 3.3V, TA = 25°C
- Ioff supports live insertion, partial power down mode, and back drive protection
- Support mixed-mode voltage operation on all ports
- Latch-up performance exceeds 250mAper JESD 17
The SN74LV126A quadruple bus buffer gates are designed for 2V to 5.5V VCC operation.
These quadruple bus buffer gates are designed for 2V to 5.5V VCC operation.
The SN74LV126A devices feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
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| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | SN74LV126A Quadruple Bus Buffer Gates With 3-State Outputs datasheet (Rev. J) | PDF | HTML | 2024/4/4 |
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14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOIC (D) | 14 | Ultra Librarian |
| TVSOP (DGV) | 14 | Ultra Librarian |
| SOP (NS) | 14 | Ultra Librarian |
| TSSOP (PW) | 14 | Ultra Librarian |
| SSOP (DB) | 14 | Ultra Librarian |