SN74LV06A
- VCC operation of 2 V to 5.5 V
- Max tpd of 6.5 ns at 5 V
- Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
- Typical VOHV (Output VOH Undershoot) > 2.3 V at VCC = 3.3 V, TA = 25°C
- Outputs are disabled during power up and power down with inputs tied to VCC
- Support mixed-mode voltage operation on all ports
- Ioff supports live insertion, partial power down mode, and back drive protection
- Latch-up performance exceeds 100 mA per JESD 78, Class II
These hex inverter buffers/drivers are designed for 2 V to 5.5 V VCC operation.
The SN74LV06A device performs the Boolean function Y = A in positive logic.
The open-drain output require pull-up resistors to perform correctly and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions.
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| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | SN74LV06A Hex Inverter Buffers/Drivers With Open-Drain Outputs datasheet (Rev. K) | PDF | HTML | 2023/3/16 |
設計與開發
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開發板
14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOIC (D) | 14 | Ultra Librarian |
| TSSOP (PW) | 14 | Ultra Librarian |
| SOP (NS) | 14 | Ultra Librarian |
| TVSOP (DGV) | 14 | Ultra Librarian |
| SSOP (DB) | 14 | Ultra Librarian |