SN74LS540
- 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers
- P-N-P Inputs Reduce D-C Loading
- Hysteresis at Inputs Improves Noise Margins
- Data Flow-thru Pinout (All Inputs on Opposite Side from Outputs)
These octal buffers and line drivers are designed to have the performance of the popular SN54LS240/SN74LS240 series and, at the same time, offer a pinout having the inputs and outputs on opposite sides of the package. This arrangement greatly enhances printed circuit board layout.
The three-state control gate is a 2-input NOR such that if either G1\ or G2\ are high, all eight outputs are in the high-impedance state.
The 'LS540 offers inverting data and the 'LS541 offers true data at the outputs.
The SN54LS540 and SN54LS541 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LS540 and SN74LS541 are characterized for operation from 0°C to 70°C.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | Octal Buffers And Line Drivers With 3-State Outputs datasheet | 1988/3/1 |
設計與開發
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14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOP (NS) | 20 | Ultra Librarian |
| PDIP (N) | 20 | Ultra Librarian |
| SSOP (DB) | 20 | Ultra Librarian |
| SOIC (DW) | 20 | Ultra Librarian |