SN74HCT540
- Operating Voltage Range of 4.5 V to 5.5 V
- Low Power Consumption, 80-µA Max ICC
- Typical tpd = 12 ns
- ±6-mA Output Drive at 5 V
- Low Input Current of 1 µA Max
- Inputs Are TTL-Voltage Compatible
- High-Current 3-State Outputs Interface Directly With System Bus or Can Drive Up To 15 LSTTL Loads
- Data Flow-Through Pinout (All Inputs on Opposite Side From Outputs)
These octal buffers and line drivers are designed to have the performance of the HCT240 devices and a pinout with inputs and outputs on opposite sides of the package. This arrangement greatly facilitates printed circuit board layout.
The 3-state control gate is a 2-input NOR. If either output-enable (OE1\ or OE2\) input is high, all eight outputs are in the high-impedance state. The HCT540 devices provide inverted data at the outputs.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | SN54HCT540, SN74HCT540 datasheet (Rev. C) | 2003/3/18 |
設計與開發
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14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOIC (DW) | 20 | Ultra Librarian |
| PDIP (N) | 20 | Ultra Librarian |