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邏輯和電壓轉換
正反器、鎖存器和暫存器
D 型正反器

SN74HCT377

現行

具有時脈賦能端的八路 D 型正反器

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產品規格表

SN74HCT377

現行
產品規格表 立即訂購

產品詳細資料

Number of channels 8 Technology family HCT Input type TTL-Compatible CMOS Output type Push-Pull Clock frequency (max) (MHz) 35 IOL (max) (mA) 4 IOH (max) (mA) -4 Supply current (max) (µA) 80 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 8 Technology family HCT Input type TTL-Compatible CMOS Output type Push-Pull Clock frequency (max) (MHz) 35 IOL (max) (mA) 4 IOH (max) (mA) -4 Supply current (max) (µA) 80 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -40 to 85 Rating Catalog
SOIC (DW) 20 131.84 mm² (12.8 mm × 10.3 mm) PDIP (N) 20 228.702 mm² (24.33 mm × 9.4 mm)
  • Operating Voltage Range of 4.5 V to 5.5 V
  • Outputs Can Drive Up To 10 LSTTL Loads
  • Low Power Consumption, 80-&miccro;A Max ICC
  • Typical tpd = 12 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max
  • Inputs Are TTL-Voltage Compatible
  • Contain Eight Flip-Flops With Single-Rail Outputs
  • Clock Enable Latched to Avoid False Clocking
  • Applications Include:
    • Buffer/Storage Registers
    • Shift Registers
    • Pattern Generators
  • Operating Voltage Range of 4.5 V to 5.5 V
  • Outputs Can Drive Up To 10 LSTTL Loads
  • Low Power Consumption, 80-&miccro;A Max ICC
  • Typical tpd = 12 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max
  • Inputs Are TTL-Voltage Compatible
  • Contain Eight Flip-Flops With Single-Rail Outputs
  • Clock Enable Latched to Avoid False Clocking
  • Applications Include:
    • Buffer/Storage Registers
    • Shift Registers
    • Pattern Generators

These devices are positive-edge-triggered D-type flip-flops. The ’HCT377 devices are similar to the ’'HCT273 devices, but feature a latched clock-enable (CLKEN)\ input instead of a common clear.

Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse if CLKEN\ is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. These devices are designed to prevent false clocking by transitions at CLKEN\.

These devices are positive-edge-triggered D-type flip-flops. The ’HCT377 devices are similar to the ’'HCT273 devices, but feature a latched clock-enable (CLKEN)\ input instead of a common clear.

Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse if CLKEN\ is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. These devices are designed to prevent false clocking by transitions at CLKEN\.
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SN74HC377 現行 具有時脈賦能端的八路 D 型正反器 Voltage range 2V to 6V, average propagation delay 20ns, average drive strength 8mA

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 SN54HCT377, SN74HCT377 datasheet (Rev. D) 2003/3/18

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