SN74HCS164-Q1

現行

車用 8 位元序列輸入/平行輸出移位暫存器

立即訂購

產品規格表

document-pdfAcrobat SN74HCS164-Q1 Automotive 8-Bit Parallel-Out Serial Shift Registers With Schmitt-Trigger Inputs datasheet (Rev. C) (英文) PDF | HTML

SN74HCS164-Q1

現行

產品規格表

立即訂購

產品詳細資料

Configuration

Serial-in, Parallel-out

Bits (#)

8

Technology family

HCS

Input type

Schmitt-Trigger

Output type

Push-Pull

Clock frequency (MHz)

62

IOL (max) (mA)

7.8

IOH (max) (mA)

-7.8

Supply current (max) (µA)

2

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-40 to 125

Rating

Automotive

Configuration

Serial-in, Parallel-out

Bits (#)

8

Technology family

HCS

Input type

Schmitt-Trigger

Output type

Push-Pull

Clock frequency (MHz)

62

IOL (max) (mA)

7.8

IOH (max) (mA)

-7.8

Supply current (max) (µA)

2

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-40 to 125

Rating

Automotive

SOT-23-THN (DYY)

14

13.692 mm² (4.2 mm × 3.26 mm)

TSSOP (PW)

14

32 mm² (5 mm × 6.4 mm)

SOIC (D)

14

51.9 mm² (8.65 mm × 6 mm)

WQFN (BQA)

14

7.5 mm² (3 mm × 2.5 mm)

AEC-Q100 qualified for automotive applications:
- Device temperature grade 1: –40°C to +125°C, T_A
- Device HBM ESD Classification Level 2
- Device CDM ESD Classifcation Level C6
Wide operating voltage range: 2 V to 6 V
Schmitt-trigger inputs allow for slow or noisy input signals
Low power consumption
- Typical I_CC of 100 nA
- Typical input leakage current of ±100 nA
±7.8-mA output drive at 6 V

AEC-Q100 qualified for automotive applications:
- Device temperature grade 1: –40°C to +125°C, T_A
- Device HBM ESD Classification Level 2
- Device CDM ESD Classifcation Level C6
Wide operating voltage range: 2 V to 6 V
Schmitt-trigger inputs allow for slow or noisy input signals
Low power consumption
- Typical I_CC of 100 nA
- Typical input leakage current of ±100 nA
±7.8-mA output drive at 6 V

The SN74HCS164-Q1 device contains an 8-bit shift register with AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK. All inputs include Schmitt-triggers, eliminating any erroneous data outputs due to slow-edged or noisy input signals.

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重要文件	類型	標題	格式選項	日期
*	資料表	SN74HCS164-Q1 Automotive 8-Bit Parallel-Out Serial Shift Registers With Schmitt-Trigger Inputs datasheet (Rev. C)	PDF \| HTML	2021/12/16
	Application brief	Using Linear Interpolation to Estimate Specification Values	PDF \| HTML	2026/4/13
	Application brief	Optimizing Body Control Modules (BCMs) Using Logic and Translation	PDF \| HTML	2022/10/19
	應用說明	Designing with Shift Registers	PDF \| HTML	2022/7/14