SN74HC573A
- Wide Operating Voltage Range from 2 V to 6 V
- High-Current 3-State Outputs Drive Bus Lines Directly up to 15 LSTTL Loads
- Low Power Consumption: 80-µA Maximum ICC
- Typical tpd = 21 ns
- ±6-mA Output Drive at 5 V
- Low Input Current: 1 µA (Maximum)
- Bus-Structured Pinout
The SNx4HC573A devices are octal transparent D-type latches that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up.
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| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | SNx4HC573A Octal Transparent D-Type Latches With 3-State Outputs datasheet (Rev. G) | PDF | HTML | 2022/4/20 | ||
| 應用說明 | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 2022/12/15 |
設計與開發
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開發板
14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TSSOP (PW) | 20 | Ultra Librarian |
| SOIC (DW) | 20 | Ultra Librarian |
| SSOP (DB) | 20 | Ultra Librarian |
| PDIP (N) | 20 | Ultra Librarian |