SN74HC273
- Wide operating voltage range of 2 V to 6 V
- Outputs can drive up to 10 LSTTL loads
- Low power consumption, 80-µA maximum ICC
- Typical tpd = 12 ns
- ±4-mA output drive at 5 V
- Low input current of 1-µA maximum
- Contain eight flip-flops with single-rail outputs
- Direct clear input
- Individual data input to each flip-flop
- On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
The SNx4HC273 devices are positive-edge-triggered D-type flip-flops with a direct active low clear ( CLR) input.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.
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| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | SNx4HC273 Octal D-Type Flip-Flops With Clear datasheet (Rev. F) | PDF | HTML | 2022/4/21 | ||
| Application brief | Using Linear Interpolation to Estimate Specification Values | PDF | HTML | 2026/4/13 | |||
| 應用說明 | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 2022/12/15 |
設計與開發
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開發板
14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| PDIP (N) | 20 | Ultra Librarian |
| SSOP (DB) | 20 | Ultra Librarian |
| TSSOP (PW) | 20 | Ultra Librarian |
| SOIC (DW) | 20 | Ultra Librarian |
| SOP (NS) | 20 | Ultra Librarian |