SN74HC138
- Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems
- Wide Operating Voltage Range (2 V to 6 V)
- Outputs Can Drive Up To 10 LSTTL Loads
- Low Power Consumption, 80-µA Maximum ICC
- Typical tpd = 15 ns
- ±4-mA Output Drive at 5 V
- Low Input Current of 1-µA Maximum
- Active Low Outputs ( Selected Output is Low)
- Incorporate Three Enable Inputs to Simplify Cascading or Data Reception
The SNx4HC138 devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories using a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.
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技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | SNx4HC138 3-Line To 8-Line Decoders/Demultiplexers datasheet (Rev. G) | PDF | HTML | 2021/10/8 | ||
| Application brief | Using Linear Interpolation to Estimate Specification Values | PDF | HTML | 2026/4/13 |
設計與開發
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14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SSOP (DB) | 16 | Ultra Librarian |
| SOIC (D) | 16 | Ultra Librarian |
| TSSOP (PW) | 16 | Ultra Librarian |
| PDIP (N) | 16 | Ultra Librarian |
| SOP (NS) | 16 | Ultra Librarian |