首頁 邏輯和電壓轉換 正反器、鎖存器和暫存器 D 型正反器
首頁
邏輯和電壓轉換
正反器、鎖存器和暫存器
D 型正反器

SN74F175

現行

具有清除功能的四路 D 型正反器

立即訂購
產品規格表

SN74F175

現行
產品規格表 立即訂購

產品詳細資料

Number of channels 4 Technology family F Input type Bipolar Output type Push-Pull Clock frequency (max) (MHz) 100 IOL (max) (mA) 20 IOH (max) (mA) -1 Supply current (max) (µA) 34000 Features Very high speed (tpd 5-10ns) Operating temperature range (°C) 0 to 70 Rating Catalog
Number of channels 4 Technology family F Input type Bipolar Output type Push-Pull Clock frequency (max) (MHz) 100 IOL (max) (mA) 20 IOH (max) (mA) -1 Supply current (max) (µA) 34000 Features Very high speed (tpd 5-10ns) Operating temperature range (°C) 0 to 70 Rating Catalog
SOIC (D) 16 59.4 mm² (9.9 mm × 6 mm) PDIP (N) 16 181.42 mm² (19.3 mm × 9.4 mm) SOP (NS) 16 79.56 mm² (10.2 mm × 7.8 mm)
  • Contains Four Flip-Flops With Double-Rail Outputs
  • Buffered Clock and Direct Clear Inputs
  • Applications Include:
    • Buffer/Storage Registers
    • Shift Registers
    • Pattern Generators
  • Contains Four Flip-Flops With Double-Rail Outputs
  • Buffered Clock and Direct Clear Inputs
  • Applications Include:
    • Buffer/Storage Registers
    • Shift Registers
    • Pattern Generators

This positive-edge-triggered flip-flop utilizes TTL circuitry to implement D-type flip-flop logic with a direct clear (CLR)\ input. Information at the data (D) inputs meeting setup-time requirements is transferred to outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.

This positive-edge-triggered flip-flop utilizes TTL circuitry to implement D-type flip-flop logic with a direct clear (CLR)\ input. Information at the data (D) inputs meeting setup-time requirements is transferred to outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
filter 尋找其它 D 型正反器
下載

您可能會感興趣的類似產品

open-in-new 比較替代產品
針腳對針腳的功能與所比較的裝置相同。
CD74ACT175 現行 具有重設功能的四路 D 型正反器 Voltage range 4.5V to 5.5V, average propagation delay 8ns, average drive strength 24mA

技術文件

找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 1
重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 Quadruple D-Type Flip-Flop With Clear datasheet (Rev. B) 2002/5/22

訂購與品質

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

以英文檢視所有論壇主題

內容係由 TI 和社群貢獻者依「現狀」提供，且不構成 TI 規範。檢視使用條款。

若有關於品質、封裝或訂購 TI 產品的問題，請參閱 TI 支援。​​​​​​​​​​​​​​