SN74F112
- Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs
The SN74F112 contains two independent J-K negative-edge-triggered
flip-flops. A low level at the preset (
) or clear (
) inputs sets or resets the outputs
regardless of the levels of the other inputs. When and are inactive (high), data at the J
and K inputs meeting the setup time requirements is transferred to
the outputs on the negative-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not directly related to
the rise time of the clock pulse. Following the hold-time interval,
data at the J and K inputs may be changed without affecting the
levels at the outputs. The SN74F112 can perform as a toggle flip-flop
by tying J and K high.
The SN74F112 is characterized for operation from 0°C to 70°C.
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| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset datasheet (Rev. A) | 1993/10/1 |