SN74CBTLV3253
- Functionally Equivalent to QS3253
- 5Ω Switch Connection Between Two Ports
- Rail-to-Rail Switching on Data I/O Ports
- Ioff Supports Partial-Power-Down Mode Operation
- Latch-Up Performance Exceeds 100mA Per JESD 78, Class II
The SN74CBTLV3253 device is a dual 1-of-4 high-speed FET multiplexer and demultiplexer. The low ON-state resistance of the switch allows connections to be made with minimal propagation delay.
The select (S0, S1) inputs control the data flow. The FET multiplexers/demultiplexers are disabled when the associated output-enable ( OE) input is high.
The SN74CBTLV3253 device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current cannot backflow through the device when it is powered down. The device has isolation during power off.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | SN74CBTLV3253 Low-Voltage Dual 1-of-4 FET Multiplexer/Demultiplexer datasheet (Rev. K) | PDF | HTML | 2026/7/15 | ||
| 應用說明 | Selecting the Correct Texas Instruments Signal Switch (Rev. E) | PDF | HTML | 2022/6/2 | |||
| 應用說明 | Multiplexers and Signal Switches Glossary (Rev. B) | PDF | HTML | 2021/12/1 | |||
| Application brief | Eliminate Power Sequencing with Powered-off Protection Signal Switches (Rev. C) | PDF | HTML | 2021/1/6 |
設計與開發
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LEADED-ADAPTER1 — 適用於快速測試 TI 的 5、8、10、16 及 24 針腳引線封裝的表面貼裝至 DIP 接頭適配器
EVM-LEADED1 板可用於快速測試和搭建 TI 常見的有引腳封裝 此電路板具備板上配置，可將 TI 的 D、DBQ、DCT、DCU、DDF、DGS、DGV 和 PW 表面黏著封裝轉換為 100mil DIP 排針。
LEADLESS-ADAPTER1 — 用於測試 TI 的 6、8、10、12、14、16 和 20 針腳無引線封裝的表面貼裝至 DIP 接頭適配器
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TSSOP (PW) | 16 | Ultra Librarian |
| VQFN (RGY) | 16 | Ultra Librarian |
| SOIC (D) | 16 | Ultra Librarian |
| TVSOP (DGV) | 16 | Ultra Librarian |
| SSOP (DBQ) | 16 | Ultra Librarian |
訂購與品質
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