SN74CBT3126

現行

具有 st&ard '126 型針腳的 5-V、1:1 (SPST)、4 通道通用型 FET 匯流排開關

立即訂購

產品規格表

document-pdfAcrobat SN74CBT3126 datasheet (Rev. K) (英文)

SN74CBT3126

現行

產品規格表

立即訂購

產品詳細資料

Protocols

Analog, I2C, I2S, JTAG, RGMII, SPI, TDM, UART

Configuration

1:1 SPST

Number of channels

4

Bandwidth (MHz)

200

Ron (typ) (mΩ)

5000

Input/output voltage (min) (V)

0

Input/output voltage (max) (V)

5.5

Operating temperature range (°C)

-40 to 85

Input/output continuous current (max) (mA)

128

COFF (typ) (pF)

4

OFF-state leakage current (max) (µA)

1

Ron (max) (mΩ)

22000

VIH (min) (V)

2

VIL (max) (V)

0.8

Rating

Catalog

Protocols

Analog, I2C, I2S, JTAG, RGMII, SPI, TDM, UART

Configuration

1:1 SPST

Number of channels

4

Bandwidth (MHz)

200

Ron (typ) (mΩ)

5000

Input/output voltage (min) (V)

0

Input/output voltage (max) (V)

5.5

Operating temperature range (°C)

-40 to 85

Input/output continuous current (max) (mA)

128

COFF (typ) (pF)

4

OFF-state leakage current (max) (µA)

1

Ron (max) (mΩ)

22000

VIH (min) (V)

2

VIL (max) (V)

0.8

Rating

Catalog

TSSOP (PW)

14

32 mm² (5 mm × 6.4 mm)

SOIC (D)

14

51.9 mm² (8.65 mm × 6 mm)

SSOP (DBQ)

16

29.4 mm² (4.9 mm × 6 mm)

SSOP (DB)

14

48.36 mm² (6.2 mm × 7.8 mm)

VQFN (RGY)

14

12.25 mm² (3.5 mm × 3.5 mm)

Standard ’126-Type Pinout (D, DB, DGV, and PW Packages)
5- Switch Connection Between Two Ports
TTL-Compatible Input Levels
Latch-Up Performance Exceeds 250 mA Per JESD 17

Standard ’126-Type Pinout (D, DB, DGV, and PW Packages)
5- Switch Connection Between Two Ports
TTL-Compatible Input Levels
Latch-Up Performance Exceeds 250 mA Per JESD 17

The SN74CBT3126 quadruple FET bus switch features independent line switches. Each switch is disabled when the associated output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pullup resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

The SN74CBT3126 quadruple FET bus switch features independent line switches. Each switch is disabled when the associated output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pullup resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

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重要文件	類型	標題	格式選項	下載最新的英文版本		日期
*	資料表	SN74CBT3126 datasheet (Rev. K)				2003/10/6

SN74CBT3126

具有 st&ard '126 型針腳的 5-V、1:1 (SPST)、4 通道通用型 FET 匯流排開關

SN74CBT3126

產品詳細資料

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具備升級功能，可直接投入使用替代所比較的裝置。

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