產品詳細資料

Protocols Analog Configuration 1:1 SPST Number of channels 8 Bandwidth (MHz) 100 Ron (typ) (mΩ) 5000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 5.5 Operating temperature range (°C) -40 to 85 ESD CDM (kV) 1 Input/output continuous current (max) (mA) 128 COFF (typ) (pF) 5 CON (typ) (pF) 5 OFF-state leakage current (max) (µA) 10 Ron (max) (mΩ) 8500 VIH (min) (V) 1.7 VIL (max) (V) 0.8 Rating Catalog
Protocols Analog Configuration 1:1 SPST Number of channels 8 Bandwidth (MHz) 100 Ron (typ) (mΩ) 5000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 5.5 Operating temperature range (°C) -40 to 85 ESD CDM (kV) 1 Input/output continuous current (max) (mA) 128 COFF (typ) (pF) 5 CON (typ) (pF) 5 OFF-state leakage current (max) (µA) 10 Ron (max) (mΩ) 8500 VIH (min) (V) 1.7 VIL (max) (V) 0.8 Rating Catalog
SOIC (DW) 20 131.84 mm² (12.8 mm × 10.3 mm) TSSOP (PW) 20 41.6 mm² (6.5 mm × 6.4 mm) SSOP (DBQ) 20 51.9 mm² (8.65 mm × 6 mm) VSSOP (DGS) 20 24.99 mm² (5.1 mm × 4.9 mm) TVSOP (DGV) 20 32 mm² (5 mm × 6.4 mm)
  • Standard ’245-type pinout
  • Output voltage translation tracks VCC
  • Supports mixed-mode signal operation on all data I/O ports
    • 5V Input down to 3.3V output level shift with 3.3V VCC
    • 5V/3.3V input down to 2.5V output level shift with 2.5V VCC
  • 5V-tolerant I/Os with device powered up or powered down
  • Bidirectional data flow with near-zero propagation delay
  • Low ON-state resistance (ron) characteristics (ron = 5Ω typical)
  • Low Input, output capacitance minimizes loading (Cio(OFF) = 5pF typical)
  • Data and control inputs provide undershoot clamp diodes
  • Low power consumption (ICC = 40µA maximum)
  • VCC operating range from 2.3V to 3.6V
  • Data I/Os support 0 to 5V signaling levels (0.8V, 1.2V, 1.5V, 1.8V, 2.5V, 3.3V, 5V)
  • Control inputs can be driven by TTL or 5V/3.3V CMOS outputs
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 250mA per JESD 17
  • ESD performance tested per JESD 22
    • 2000V human-body model (A114-B, Class II)
    • 1000V charged-device model (C101)
  • Designed for low-power portable equipment
  • Standard ’245-type pinout
  • Output voltage translation tracks VCC
  • Supports mixed-mode signal operation on all data I/O ports
    • 5V Input down to 3.3V output level shift with 3.3V VCC
    • 5V/3.3V input down to 2.5V output level shift with 2.5V VCC
  • 5V-tolerant I/Os with device powered up or powered down
  • Bidirectional data flow with near-zero propagation delay
  • Low ON-state resistance (ron) characteristics (ron = 5Ω typical)
  • Low Input, output capacitance minimizes loading (Cio(OFF) = 5pF typical)
  • Data and control inputs provide undershoot clamp diodes
  • Low power consumption (ICC = 40µA maximum)
  • VCC operating range from 2.3V to 3.6V
  • Data I/Os support 0 to 5V signaling levels (0.8V, 1.2V, 1.5V, 1.8V, 2.5V, 3.3V, 5V)
  • Control inputs can be driven by TTL or 5V/3.3V CMOS outputs
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 250mA per JESD 17
  • ESD performance tested per JESD 22
    • 2000V human-body model (A114-B, Class II)
    • 1000V charged-device model (C101)
  • Designed for low-power portable equipment

The SN74CB3T3245 device is a high-speed, TTL-compatible, 8-bit FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O ports by providing voltage translation that tracks VCC.

The SN74CB3T3245 device is a high-speed, TTL-compatible, 8-bit FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O ports by providing voltage translation that tracks VCC.

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 SN74CB3T3245 8-Bit FET Bus Switch 2.5V and 3.3V Low-Voltage With 5V-Tolerant Level Shifter datasheet (Rev. E) PDF | HTML 2026/5/5
應用說明 Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 2022/6/2
應用說明 Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 2021/12/1
Application brief Eliminate Power Sequencing with Powered-off Protection Signal Switches (Rev. C) PDF | HTML 2021/1/6

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HSPICE Model for SN74CB3T3245

SCDJ028.ZIP (99 KB) - HSpice 模型
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SN74CB3T3245 IBIS Model

SCDM055.ZIP (26 KB) - IBIS 模型
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
SOIC (DW) 20 Ultra Librarian
TSSOP (PW) 20 Ultra Librarian
SSOP (DBQ) 20 Ultra Librarian
VSSOP (DGS) 20 Ultra Librarian
TVSOP (DGV) 20 Ultra Librarian

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