SN74AXCH8T245
- Qualified Fully Configurable Dual-Rail Design Allows Each Port to Operate With a Power Supply Range From 0.65 V to 3.6 V
- Operating Temperature From –40°C to +125°C
- Bus-hold on Data Inputs Eliminates the Need for External Pullup or Pulldown Resistors
- Multiple Direction Control Pins to Allow Simultaneous Up and Down Translation
- Up to 380 Mbps support when translating from 1.8 V to 3.3 V
- VCC Isolation Feature to Effectively Isolate Both Buses in a Power-Down Scenario
- Partial Power-Down Mode to Limit Backflow Current in a Power-Down Scenario
- Compatible With SN74AVCH8T245 and 74AVCH8T245 Level Shifters
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 8000-V Human-Body Model
- 1000-V Charged-Device Model
The SN74AXCH8T245 device is an 8-bit non-inverting bus transceiver that resolves voltage level mismatch between devices operating at the latest voltage nodes (0.7 V, 0.8 V, and 0.9 V) and devices operating at industry standard voltage nodes (1.8 V, 2.5 V, 3.3 V) and vice versa.
The device operates by using two independent power-supply rails (VCCA and VCCB) . Data pins A1 through A8 are designed to track VCCA, which accepts any supply voltage from 0.65 V to 3.6 V. Data pins B1 through B8 are designed to track VCCB, which accepts any supply voltage from 0.65 V to 3.6 V. Additionally the SN74AXCH8T245 is compatible with a single-supply system.
The SN74AXCH8T245 device is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level of the direction-control inputs (DIR1 and DIR2). The output-enable (OE) input is used to disable the outputs so the buses are effectively isolated.
The SN74AXCH8T245 device is designed so the control pins (DIR and OE) are referenced to VCCA.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pull-up or pull-down resistors with the bus-hold circuitry is not recommended. If a supply is present for VCCA or VCCB, the bus-hold circuitry always remains active on all A and B ports respectively, independent of the direction control or output enable.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.
The VCC isolation feature ensures that if either VCC input supply is below 100 mV, all level shifter outputs are disabled and placed into a high-impedance state. To ensure the high-impedance state of the level shifter I/Os during power up or power down, OE should be tied to VCCA through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | SN74AXCH8T245 8-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation, Tri-State Outputs, and Bus-Hold Circuitry datasheet (Rev. A) | PDF | HTML | 2019/1/7 | ||
| 應用說明 | Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators | PDF | HTML | 2024/10/2 | |||
| 應用說明 | Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators | PDF | HTML | 2024/7/12 | |||
| 應用說明 | Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) | PDF | HTML | 2024/7/3 | |||
| 應用說明 | Low Voltage Translation for SPI, UART, RGMII, JTAG Interfaces (Rev. B) | PDF | HTML | 2021/3/29 | |||
| 應用說明 | Glitch free power sequencing with AXC level translators (Rev. A) | 2018/9/20 | ||||
| 應用說明 | An Overview of Bus-Hold Circuit and the Applications (Rev. B) | 2018/9/17 |
設計與開發
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RHL) | 24 | Ultra Librarian |
| TSSOP (PW) | 24 | Ultra Librarian |