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SN74AVCH4T245
- Control inputs VIH/VIL levels are referenced to VCCA voltage
- Fully configurable dual-rail design allows each port to operate over the full 1.2V to 3.6V power-supply range
- I/Os Are 4.6V Tolerant
- Ioff supports partial power-down-mode operation
- Bus hold on data inputs eliminates the need for external pull-up/pull-down resistors
- Supports data rate up to:
- 380Mbps (1.8V to 3.3V Translation)
- 200Mbps (<1.8V to 3.3V Translation)
- 200Mbps (Translate to 2.5V or 1.8V)
- 150Mbps (Translate to 1.5V)
- 100Mbps (Translate to 1.2V)
- Latch-up performance exceeds 100mA per JESD 78, class II
- ESD protection exceeds JESD 22:
- 8000V Human Body Model (A114-A)
- 200V Machine Model (A115-A)
- 1000V Charged-Device Model (C101)
This 4-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2V to 3.6V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2V to 3.6V. The SN74AVCH4T245 is optimized to operate with VCCA/VCCB set at 1.2V to 3.6V. It is operational with VCCA/VCCB as low as 1.2V. This allows for universal low voltage bidirectional translation between any of the 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes.
The SN74AVCH4T245 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.
The SN74AVCH4T245 device control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by VCCA.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The VCC isolation feature is designed so that if either VCC input is at GND, then both ports are in the high-impedance state. The bus-hold circuitry on the powered-up side always stays active.
Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state. Use of pull-up or pull-down resistors with the bus-hold circuitry is not recommended. The bus-hold circuitry on the powered-up side always stays active.
To put the device in the high-impedance state during power up or power down, tie the OE pin to VCC through a pull-up resistor; the current-sinking capability of the driver determines the minimum value of the resistor.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | SN74AVCH4T245 4-Bit Dual-Supply Bus Transceiver With Configurable Level-Shifting, Voltage Translation, and 3-State Outputs datasheet (Rev. F) | PDF | HTML | 2025/2/13 | ||
| 應用說明 | Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators | PDF | HTML | 2024/10/2 | |||
| 應用說明 | Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators | PDF | HTML | 2024/7/12 | |||
| 應用說明 | Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) | PDF | HTML | 2024/7/3 | |||
| 選擇指南 | Voltage Translation Buying Guide (Rev. A) | 2021/4/15 |
設計與開發
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