SN74AUP1G08-Q1
- AEC-Q100 Qualified with the Following Results:
- Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range
- Device HBM ESD Classification Level H2
- Device CDM ESD Classification Level C3B
- Available in the Texas Instruments NanoStar Package
- Low Static-Power Consumption:
ICC = 0.9 µA Max - Low Dynamic-Power Consumption:
Cpd = 4.3 pF Typ at 3.3 V - Low Input Capacitance: Ci = 1.5 pF Typ
- Low Noise: Overshoot and Undershoot
< 10% of VCC - Ioff Supports Partial-Power-Down Mode Operation
- Schmitt-Trigger Action Allows Slow Input Transition and Better
Switching Noise Immunity at the Input (Vhys = 250 mV, Typ at
3.3 V) - Wide Operating VCC Range of 0.8 V to 3.6 V
- Optimized for 3.3-V Operation
- 3.6-V Input/Output (I/O) Tolerant to Support Mixed-Mode Signal Operation
- tpd = 4.3 ns Max at 3.3 V
- Suitable for Point-to-Point Applications
- Latch-Up Performance Exceeds 100 mA Per JESD-78, Class II
NanoStar is a trademark of Texas Instruments.
The AUP family is TIs premier solution to the low-power needs of the industry in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).
This single 2-input positive-AND gate performs the Boolean function: Y = A B or Y = A\ + B\ in positive logic.
NanoStar package technology is a major breakthrough in integrated circuit (IC) packaging concepts, because it uses the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | LOW-POWER SINGLE 2-INPUT POSITIVE AND GATE datasheet | 2012/12/12 | |||
| 更多文件說明 | Automotive Logic Devices Brochure | 2014/8/27 |
設計與開發
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|---|---|---|
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