SN74AUC1GU04
- Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II - ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
- Available in the Texas Instruments
NanoFree™ Package - Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
- Sub-1-V Operable
- Max tpd of 2.4 ns at 1.8 V
- Low Power Consumption, 10-µA Max ICC
- ±8-mA Output Drive at 1.8 V
- Unbuffered Output
- Ioff Supports Partial Power Down Mode and Back Drive Protection
This single inverter gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.
The SN74AUC1GU04 device contains one inverter with an unbuffered output and performs the Boolean function Y = A.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
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| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | SN74AUC1GU04 Single Inverter Gate datasheet (Rev. M) | PDF | HTML | 2017/6/8 | ||
| Application brief | Generate a Clock Signal from a Crystal Oscillator | PDF | HTML | 2020/10/8 | |||
| 應用說明 | Use of the CMOS Unbuffered Inverter in Oscillator Circuits | 2003/11/6 |
設計與開發
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開發板
5-8-LOGIC-EVM — 適用於 5 針腳至 8 針腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評估模組
靈活的 EVM 旨在支援任何針腳數為 5 至 8 支且採用 DCK、DCT、DCU、DRL 或 DBV 封裝的裝置。
使用指南:
PDF
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| DSBGA (YZP) | 5 | Ultra Librarian |
| SOT-23 (DBV) | 5 | Ultra Librarian |
| SOT-SC70 (DCK) | 5 | Ultra Librarian |