SN74ALVCH374

現行

具有 3 態輸出的八路正緣觸發 D 型正反器

立即訂購

產品規格表

document-pdfAcrobat SN74ALVCH374 datasheet (Rev. G) (英文)

SN74ALVCH374

現行

產品規格表

立即訂購

產品詳細資料

Number of channels

8

Technology family

ALVC

Input type

Standard CMOS

Output type

3-State

Clock frequency (max) (MHz)

150

IOL (max) (mA)

24

IOH (max) (mA)

-24

Supply current (max) (µA)

10

Features

Balanced outputs, Bus-hold, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Number of channels

8

Technology family

ALVC

Input type

Standard CMOS

Output type

3-State

Clock frequency (max) (MHz)

150

IOL (max) (mA)

24

IOH (max) (mA)

-24

Supply current (max) (µA)

10

Features

Balanced outputs, Bus-hold, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

TVSOP (DGV)

20

32 mm² (5 mm × 6.4 mm)

TSSOP (PW)

20

41.6 mm² (6.5 mm × 6.4 mm)

SOIC (DW)

20

131.84 mm² (12.8 mm × 10.3 mm)

Operates From 1.65 V to 3.6 V
Max t_pd of 3.6 ns at 3.3 V
±24-mA Output Drive at 3.3 V
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Operates From 1.65 V to 3.6 V
Max t_pd of 3.6 ns at 3.3 V
±24-mA Output Drive at 3.3 V
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

This octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V V_CC operation.

The SN74ALVCH374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

This octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V V_CC operation.

The SN74ALVCH374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

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重要文件	類型	標題	格式選項	日期
*	資料表	SN74ALVCH374 datasheet (Rev. G)		2004/9/3
	應用說明	Power-Up Behavior of Clocked Devices (Rev. B)	PDF \| HTML	2022/12/15
	應用說明	An Overview of Bus-Hold Circuit and the Applications (Rev. B)		2018/9/17