SN74ALS74A
- Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
These devices contain two independent positive-edge-triggered
D-type flip-flops. A low level at the preset (
) or clear (
) inputs sets or resets the outputs
regardless of the levels of the other inputs. When and are inactive (high), data at the
data (D) input meeting the setup-time requirements are transferred to
the outputs on the positive-going edge of the clock (CLK) pulse.
Clock triggering occurs at a voltage level and is not directly
related to the rise time of CLK. Following the hold-time interval,
data at the D input can be changed without affecting the levels at
the outputs.
The SN54ALS74A and SN54AS74A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS74A and SN74AS74A are characterized for operation from 0°C to 70°C.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset datasheet (Rev. C) | 1995/8/1 |