SN74AHCT74Q-Q1
- Qualified for Automotive Applications
- Inputs Are TTL-Voltage Compatible
- EPIC™ (Enhanced-Performance Implanted CMOS) Process
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015;
Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
EPIC is a trademark of Texas Instruments.
The SN74AHCT74Q is a dual positive-edge-triggered D-type flip-flop.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | Dual Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset datasheet (Rev. B) | 2008/4/24 | |||
| 應用說明 | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 2022/12/15 | |||
| 更多文件說明 | Automotive Logic Devices Brochure | 2014/8/27 |
設計與開發
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14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOIC (D) | 14 | Ultra Librarian |
| TSSOP (PW) | 14 | Ultra Librarian |