SN74AHCT594-Q1

現行

具有輸出暫存器的車用 8 位元移位暫存器

產品詳細資料

Configuration Serial-in Bits (#) 8 Technology family AHCT Input type TTL-Compatible CMOS Output type Push-Pull IOL (max) (mA) 8 IOH (max) (mA) -8 Supply current (max) (µA) 40 Operating temperature range (°C) -40 to 125 Rating Automotive
Configuration Serial-in Bits (#) 8 Technology family AHCT Input type TTL-Compatible CMOS Output type Push-Pull IOL (max) (mA) 8 IOH (max) (mA) -8 Supply current (max) (µA) 40 Operating temperature range (°C) -40 to 125 Rating Automotive
TSSOP (PW) 16 32 mm² (5 mm × 6.4 mm) WQFN (BQB) 16 8.75 mm² (3.5 mm × 2.5 mm)
  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1: -40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B
  • Available in wettable flank QFN (WBQA) package
  • Operating range 4.5V to 5.5V VCC
  • TTL-Compatible inputs
  • Low delay, 12.4ns max (VCC = 5V, CL = 50pF)
  • Latch-up performance exceeds 250mAper JESD 17
  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1: -40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B
  • Available in wettable flank QFN (WBQA) package
  • Operating range 4.5V to 5.5V VCC
  • TTL-Compatible inputs
  • Low delay, 12.4ns max (VCC = 5V, CL = 50pF)
  • Latch-up performance exceeds 250mAper JESD 17

The SN74AHCT594-Q1 is an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Separate clocks (RCLK, SRCLK) and direct overriding clear (RCLR, SRCLR) inputs are provided on both the shift and storage registers. A serial (QH’) output is provided for cascading purposes.

Both the shift register (SRCLK) and storage register (RCLK) clocks are positive edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register.

The SN74AHCT594-Q1 is an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Separate clocks (RCLK, SRCLK) and direct overriding clear (RCLR, SRCLR) inputs are provided on both the shift and storage registers. A serial (QH’) output is provided for cascading purposes.

Both the shift register (SRCLK) and storage register (RCLK) clocks are positive edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register.

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* 資料表 SN74AHCT594-Q1 Automotive 8-Bit Shift Register With Output Registers datasheet PDF | HTML 2024/3/11

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TSSOP (PW) 16 Ultra Librarian
WQFN (BQB) 16 Ultra Librarian

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