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移位暫存器

SN74AHCT164

現行

4.5-V 至 5.5-V 8 位元、平行輸出序列移位暫存器

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SN74AHCT164

現行
產品規格表 立即訂購

產品詳細資料

Configuration Serial-in Bits (#) 8 Technology family AHCT Input type TTL-Compatible CMOS Output type 3-State IOL (max) (mA) 8 IOH (max) (mA) -8 Supply current (max) (µA) 40 Features Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 125 Rating Catalog
Configuration Serial-in Bits (#) 8 Technology family AHCT Input type TTL-Compatible CMOS Output type 3-State IOL (max) (mA) 8 IOH (max) (mA) -8 Supply current (max) (µA) 40 Features Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 125 Rating Catalog
WQFN (BQA) 14 7.5 mm² (3 mm × 2.5 mm) TSSOP (PW) 14 32 mm² (5 mm × 6.4 mm)
  • Operating range 4.5V to 5.5V VCC
  • TTL-Compatible inputs
  • Low delay, 14ns max (VCC = 5V, CL = 50pF)
  • Latch-up performance exceeds 250mAper JESD 17
  • Operating range 4.5V to 5.5V VCC
  • TTL-Compatible inputs
  • Low delay, 14ns max (VCC = 5V, CL = 50pF)
  • Latch-up performance exceeds 250mAper JESD 17

The SN74AHCT164 is an 8-bit shift register with AND-gated serial inputs and an asynchronous clear (CLR) input. Outputs are directly connected to the internal shift register, resulting in immediate output changes as values are shifted into the register. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.

The SN74AHCT164 is an 8-bit shift register with AND-gated serial inputs and an asynchronous clear (CLR) input. Outputs are directly connected to the internal shift register, resulting in immediate output changes as values are shifted into the register. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.
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* 資料表 SN74AHCT164 8-Bit Parallel-Out Serial Shift Register datasheet PDF | HTML 2024/3/28

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WQFN (BQA) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian
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