SN74AHCT126-Q1
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AEC-Q100 qualified for automotive applications:
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Device temperature grade 1: -40°C to +125°C
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Device HBM ESD classification level 2
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Device CDM ESD classification level C4B
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Available in wettable flank QFN (WBQA) package
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Operating range of 4.5V to 5.5V
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±8mA output drive at 5V
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Inputs are TTL-voltage compatible
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Latch-up performance exceeds 250mA per JESD 17
The SN74AHCT126-Q1 device is a quadruple bus buffer gate featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. When OE is high, the respective gate passes the data from the A input to its Y output.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
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技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | SN74AHCT126-Q1 Automotive Quadruple Bus Buffer Gate with 3-State Outputs datasheet (Rev. D) | PDF | HTML | 2024/2/22 | ||
| 更多文件說明 | Automotive Logic Devices Brochure | 2014/8/27 |
設計與開發
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14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TSSOP (PW) | 14 | Ultra Librarian |
| SOIC (D) | 14 | Ultra Librarian |
| WQFN (BQA) | 14 | Ultra Librarian |