SN74AHCT126-Q1

現行

具有 TTL 相容 CMOS 輸入和 3 態輸出的車用 4 通道、4.5-V 至 5.5-V 緩衝器

產品詳細資料

Technology family AHCT Number of channels 4 IOL (max) (mA) 8 Supply current (max) (µA) 20 IOH (max) (mA) -8 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Rating Automotive Operating temperature range (°C) -40 to 125
Technology family AHCT Number of channels 4 IOL (max) (mA) 8 Supply current (max) (µA) 20 IOH (max) (mA) -8 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Rating Automotive Operating temperature range (°C) -40 to 125
TSSOP (PW) 14 32 mm² (5 mm × 6.4 mm) SOIC (D) 14 51.9 mm² (8.65 mm × 6 mm) WQFN (BQA) 14 7.5 mm² (3 mm × 2.5 mm)
  • AEC-Q100 qualified for automotive applications:

    • Device temperature grade 1: -40°C to +125°C

    • Device HBM ESD classification level 2

    • Device CDM ESD classification level C4B

  • Available in wettable flank QFN (WBQA) package

  • Operating range of 4.5V to 5.5V

  • ±8mA output drive at 5V

  • Inputs are TTL-voltage compatible

  • Latch-up performance exceeds 250mA per JESD 17

  • AEC-Q100 qualified for automotive applications:

    • Device temperature grade 1: -40°C to +125°C

    • Device HBM ESD classification level 2

    • Device CDM ESD classification level C4B

  • Available in wettable flank QFN (WBQA) package

  • Operating range of 4.5V to 5.5V

  • ±8mA output drive at 5V

  • Inputs are TTL-voltage compatible

  • Latch-up performance exceeds 250mA per JESD 17

The SN74AHCT126-Q1 device is a quadruple bus buffer gate featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. When OE is high, the respective gate passes the data from the A input to its Y output.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

The SN74AHCT126-Q1 device is a quadruple bus buffer gate featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. When OE is high, the respective gate passes the data from the A input to its Y output.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

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最新 SN74ACT125-Q1 現行 具有 TTL 相容輸入和 3 態輸出的車用 4 通道緩衝器 Voltage range 4.5V to 5.5V, average propagation delay 8ns, average drive strength 24mA
最新 SN74ACT126-Q1 現行 具有 TTL 相容輸入的車用 4.5V 至 5.5V、4 通道緩衝器 Voltage range 4.5V to 5.5V, average propagation delay 8ns, average drive strength 24mA

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 SN74AHCT126-Q1 Automotive Quadruple Bus Buffer Gate with 3-State Outputs datasheet (Rev. D) PDF | HTML 2024/2/22
更多文件說明 Automotive Logic Devices Brochure 2014/8/27

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SN74AHCT126 Behavioral SPICE Model

SCLM255.ZIP (7 KB) - PSpice 模型
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TSSOP (PW) 14 Ultra Librarian
SOIC (D) 14 Ultra Librarian
WQFN (BQA) 14 Ultra Librarian

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