SN74ABT273

現行

具有清除功能的八路邊緣觸發 D 型正反器

產品詳細資料

Number of channels 8 Technology family ABT Input type TTL-Compatible CMOS Output type Push-Pull Clock frequency (max) (MHz) 150 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (µA) 30000 Features Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 8 Technology family ABT Input type TTL-Compatible CMOS Output type Push-Pull Clock frequency (max) (MHz) 150 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (µA) 30000 Features Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
SOIC (DW) 20 131.84 mm² (12.8 mm × 10.3 mm) SOP (NS) 20 98.28 mm² (12.6 mm × 7.8 mm) TSSOP (PW) 20 41.6 mm² (6.5 mm × 6.4 mm) SSOP (DB) 20 56.16 mm² (7.2 mm × 7.8 mm) PDIP (N) 20 228.702 mm² (24.33 mm × 9.4 mm)
  • State-of-the-Art EPIC-IIBTM BiCMOS Design Significantly Reduces Power Dissipation
  • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
  • Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
  • High-Drive Outputs (-32-mA IOH, 64-mA IOL)
  • Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Plastic (N) and Ceramic (J) DIPs, and Ceramic Flat (W) Package

 

EPIC-IIB is a trademark of Texas Instruments Incorporated.

  • State-of-the-Art EPIC-IIBTM BiCMOS Design Significantly Reduces Power Dissipation
  • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
  • Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
  • High-Drive Outputs (-32-mA IOH, 64-mA IOL)
  • Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Plastic (N) and Ceramic (J) DIPs, and Ceramic Flat (W) Package

 

EPIC-IIB is a trademark of Texas Instruments Incorporated.

The 'ABT273 are 8-bit positive-edge-triggered D-type flip-flops with a direct clear () input. They are particularly suitable for implementing buffer and storage registers, shift registers, and pattern generators.

Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D input signal has no effect at the output.

The SN54ABT273 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT273 is characterized for operation from -40°C to 85°C.

 

 

The 'ABT273 are 8-bit positive-edge-triggered D-type flip-flops with a direct clear () input. They are particularly suitable for implementing buffer and storage registers, shift registers, and pattern generators.

Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D input signal has no effect at the output.

The SN54ABT273 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT273 is characterized for operation from -40°C to 85°C.

 

 

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SN74HCT273 現行 具有清除功能的八路 D 型正反器 Voltage range 4.5V to 5.5V, average propagation delay 22ns, average drive strength 4mA

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 Octal Edge-Triggered D-Type Flip-Flops With Clear datasheet (Rev. B) 1997/1/1
應用說明 Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022/12/15

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開發板

14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組

14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。

使用指南: PDF | HTML
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模擬型號

SN74ABT273 IBIS Model (Rev. B)

SCBM081 (89 KB) - IBIS 模型
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
SOIC (DW) 20 Ultra Librarian
SOP (NS) 20 Ultra Librarian
TSSOP (PW) 20 Ultra Librarian
SSOP (DB) 20 Ultra Librarian
PDIP (N) 20 Ultra Librarian

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