SN65ELT21
- 3ns (TYP) Propagation Delay
- Operating Range: VCC = 4.2 V to 5.7 V with GND = 0 V
- 24-mA TTL Output
- Deterministic Output Value for Open Input Conditions or When Inputs < 1.3 V
- Built-In Temperature Compensation
- Drop-In Compatible to the MC10ELT21, MC100ELT21
- APPLICATIONS
- Data and Clock Transmission Over Backplane
- Signaling Level Conversion for Clock or Data
The SN65ELT21 is a differential PECL-to-TTL translator. It operates on +5-V supply and ground only. The device includes circuitry to maintain Q to a low logic level when inputs are in an open condition or < 1.3 V.
The VBB pin is a reference voltage output for the device. When the device is used in single-ended mode, the unused input should be tied to VBB. This reference voltage can also be used to bias the input when it is ac coupled. When it is used, place a 0.01µF decoupling capacitor between VCC and VBB. Also limit the sink/source current to < 0.5 mA to VBB. Leave VBB open when it is not used.
The SN65ELT21 is housed in an industry standard SOIC-8 package and is also available in an optional TSSOP-8 package.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | 5-V PECL-to-TTL Translator datasheet | 2009/6/26 | |||
| 應用說明 | AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) | 2007/10/17 |
設計與開發
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOIC (D) | 8 | Ultra Librarian |
| VSSOP (DGK) | 8 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。