產品詳細資料

Function General-purpose timer Iq (typ) (mA) 2 Rating Catalog Operating temperature range (°C) -40 to 105
Function General-purpose timer Iq (typ) (mA) 2 Rating Catalog Operating temperature range (°C) -40 to 105
SOIC (D) 8 29.4 mm² (4.9 mm × 6 mm) PDIP (P) 8 92.5083 mm² (9.81 mm × 9.43 mm)
  • Timing from microseconds to hours
  • Astable or monostable operation
  • Adjustable duty cycle
  • TTL-compatible output can sink or source up to 200mA
  • On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
  • Timing from microseconds to hours
  • Astable or monostable operation
  • Adjustable duty cycle
  • TTL-compatible output can sink or source up to 200mA
  • On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

The Nx555 and Sx555 devices are precision timing circuits capable of producing accurate time delays or oscillation. In time-delay or monostable operating modes, the timed interval is controlled by a single external resistor and capacitor network. In the astable mode of operation, the frequency and duty cycle are controlled independently with two external resistors and a single external capacitor.

Each timer has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage pin (CONT). When the trigger input (TRIG) is less than the trigger level, the flip-flop is set and the output goes high. If TRIG is greater than the trigger level and the threshold input (THRES) is greater than the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) overrides all other inputs and is used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge pin (DISCH) and the ground pin (GND). Tie all unused inputs to an appropriate logic level to prevent false triggering

The output circuit is capable of sinking or sourcing current up to 200mA. Operation is specified for supplies of 5V to 15V. With a 5V supply, output levels are compatible with TTL inputs.

The Nx555 and Sx555 devices are precision timing circuits capable of producing accurate time delays or oscillation. In time-delay or monostable operating modes, the timed interval is controlled by a single external resistor and capacitor network. In the astable mode of operation, the frequency and duty cycle are controlled independently with two external resistors and a single external capacitor.

Each timer has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage pin (CONT). When the trigger input (TRIG) is less than the trigger level, the flip-flop is set and the output goes high. If TRIG is greater than the trigger level and the threshold input (THRES) is greater than the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) overrides all other inputs and is used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge pin (DISCH) and the ground pin (GND). Tie all unused inputs to an appropriate logic level to prevent false triggering

The output circuit is capable of sinking or sourcing current up to 200mA. Operation is specified for supplies of 5V to 15V. With a 5V supply, output levels are compatible with TTL inputs.

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 xx555 Precision Timers datasheet (Rev. K) PDF | HTML 2026/3/4
應用說明 Considering TI Smart DACs As an Alternative to 555 Timers PDF | HTML 2021/9/2
設計指南 AC-Coupled RS-485 Design Guide 2016/6/15
設計指南 Automatic Direction Control RS-485 Design Guide 2016/6/2

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參考設計

TIDA-01090 — RS-485 自動方向控制參考設計

TIDA-01090 參考設計可透過 RS-485 匯流排進行半雙工通訊,且無需額外的驅動器啟用/接收器啟用控制。  此設計可讓每個節點上使用的收發器在從本機微控制器 (MCU) 或通用非同步接收器/發射器 (UART) 傳送資料時,自動進入發射模式,並在資料訊框完成後轉換回接收模式。
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參考設計

TIDA-01365 — 雙向 RS-485 扇出集線器參考設計

雙向 RS-485 扇出集線器參考設計 (TIDA-01365) 記錄並測試了一種 RS-485 扇出集線器設計,其中 1:N 和 N:1 RS-485 訊號可在任何匯流排拓撲結構中進行彙總輸入和輸出。此設計也具備自動方向控制功能,可減少微控制器的接腳數,以及一個 DC 轉 DC 轉換器。其使用工業應用中常見的 24V DC 軌。
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
SOIC (D) 8 Ultra Librarian
PDIP (P) 8 Ultra Librarian

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