LP87565-Q1
- Qualified for Automotive Applications
- AEC-Q100 Qualified With the Following Results:
- Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature
- Device HBM ESD Classification Level 2
- Device CDM ESD Classification Level C4B
- Input Voltage: 2.8 V to 5.5 V
- Output Voltage: 0.6 V to 3.36 V
- Four High-Efficiency
Step-Down DC/DC Converter Cores:
- Maximum Output Current: 16 A (4 A per Phase)
- Programmable Output Voltage Slew-Rate: 0.5 mV/µs to 10 mV/µs
- Switching Frequency: 2 MHz
- Spread-Spectrum Mode and Phase Interleaving
- Configurable General Purpose I/O (GPIOs)
- I2C-Compatible Interface That Supports Standard (100 kHz), Fast (400 kHz), Fast+ (1 MHz), and High-Speed (3.4 MHz) Modes
- Interrupt Function With Programmable Masking
- Programmable Power-Good Signal (PGOOD)
- Output Short-Circuit and Overload Protection
- Overtemperature Warning and Protection
- Overvoltage Protection (OVP) and Undervoltage Lockout (UVLO)
The LP8756x-Q1 device is designed to meet the power-management requirements of the latest processors and platforms in various automotive power applications. The device contains four step-down DC/DC converter cores, which are configured as a 4-phase output, 3-phase and 1-phase outputs, 2-phase and 2-phase outputs, one 2-phase and two 1-phase outputs, or four 1-phase outputs. The device is controlled by an I2C-compatible serial interface and by enable signals.
The automatic pulse-width-modulation (PWM) to pulsed-frequency-modulation (PFM) operation (AUTO mode), together with the automatic phase adding and phase shedding, maximizes efficiency over a wide output-current range. The LP8756x-Q1 supports remote differential-voltage sensing for multiphase outputs to compensate IR drop between the regulator output and the point-of-load (POL) improving the accuracy of the output voltage. The switching clock can be forced to PWM mode and also synchronized to an external clock to minimize the disturbances.
The LP8756x-Q1 device supports load-current measurement without the addition of external current-sense resistors. The device also supports programmable start-up and shutdown delays and sequences synchronized to enable signals. The sequences can include GPIO signals to control external regulators, load switches, and processor reset. During start-up and voltage change, the device controls the output slew rate to minimize output-voltage overshoot and in-rush current.
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN-HR (RNF) | 26 | Ultra Librarian |
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