LM3881
- Easiest Method to Sequence Rails
- Power-Up and Power-Down Control
- Tiny Footprint
- Low Quiescent Current of 80 µA
- Input Voltage Range of 2.7 V to 5.5 V
- Output Invert Feature
- Timing Controlled by Small Value External
Capacitor
The LM3881 Simple Power Sequencer offers the easiest method to control power up and power down of multiple power supplies (switching or linear regulators). By staggering the start-up sequence, it is possible to avoid latch conditions or large inrush currents that can affect the reliability of the system.
Available in VSSOP-8 package, the Simple Sequencer contains a precision enable pin and three open-drain output flags. When the LM3881 is enabled, the three output flags will sequentially release, after individual time delays, thus permitting the connected power supplies to start up. The output flags will follow a reverse sequence during power down to avoid latch conditions. Time delays are defined using an external capacitor and the output flag states can be inverted by the user.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | LM3881 Simple Power Sequencer With Adjustable Timing datasheet (Rev. D) | PDF | HTML | 2014/12/10 | ||
| 選擇指南 | Power Management Guide 2018 (Rev. R) | 2018/6/25 | ||||
| 技術文章 | How to manage processor power during uncontrolled power off | PDF | HTML | 2018/6/21 | |||
| 技術文章 | Sequencing solutions: simple, reliable and cost-effective | PDF | HTML | 2017/9/27 | |||
| 技術文章 | A simple six-channel power-rail sequencing solution | PDF | HTML | 2015/11/16 | |||
| 類比設計期刊 | Power-supply sequencing for FPGAs | 2014/10/24 | ||||
| 應用說明 | Power Supply Design Considerations for Modern FPGAs (Power Designer 121) | 2010/2/2 |
設計與開發
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LM3881EVAL — 適用於 LM3881 電源序列器的評估板
The LM3881 evaluation board has been designed to connect directly to the power supplies of an existing system to enable sequencing. Upon enabling the device, the three open drain output flags will rise in sequential order, 1-2-3. Once the part is disabled, the shutdown sequence will occur in (...)
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VSSOP (DGK) | 8 | Ultra Librarian |