DRV8351-SEP
- 40V Three Phase Half-Bridge Gate driver
- Drives N-Channel MOSFETs (NMOS)
- Gate Driver Supply (GVDD): 5-15V
- MOSFET supply (SHx) supports up to 40V
- Radiation Performance
- SEL, SEB, and SET resistant up to LET = 43 MeV-cm2 /mg
- SET and SEFI characterized up to LET = 43 MeV-cm2 /mg
- TID assured for every wafer lot up to 30 krad(Si)
- TID characterized up to 30 krad(Si)
- Cross conduction event is observed during SEE and SEB. Refer to SEE report for more details.
- Space-enhanced plastic (space EP):
- Controlled Baseline
- One Assembly/Test Site
- One Fabrication site
- Extended Product Life Cycle
- Product Traceability
- Integrated Bootstrap Diodes
- Supports Inverting and Non-Inverting INLx inputs
- Bootstrap gate drive architecture
- 750mA source current
- 1.5- sink current
- Low leakage current on SHx pins (<55µA)
- Absolute maximum BSTx voltage up to 57.5V
- Supports negative transients up to -22V on SHx
- Fixed deadtime insertion of 200nS
- Supports 3.3V and 5V logic inputs with 20V Abs max
- 4nS typical propagation delay matching
- Compact TSSOP package
- Efficient system design with Power Blocks
- Integrated protection features
- BST undervoltage lockout (BSTUV)
- GVDD undervoltage (GVDDUV)
DRV8351-SEP is a three phase half-bridge gate driver, capable of driving high-side and low-side N-channel power MOSFETs. The DRV8351-SEPD generates the correct gate drive voltages using an integrated bootstrap diode and external capacitor for the high-side MOSFETs. GVDD is used to generate gate drive voltage for the low-side MOSFETs. The Gate Drive architecture supports peak up to 750mA source and 1.5A sink currents.
The phase pins SHx are able to tolerate significant negative voltage transients; while high side gate driver supply BSTx and GHx can support higher positive voltage transients (57.5V) abs max voltage which improve the robustness of the system. Small propagation delay and delay matching specifications minimize the dead-time requirement which further improves efficiency. Undervoltage protection is provided for both low and high sides through GVDD and BST undervoltage lockout.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | DRV8351-SEP: 40V Three-Phase BLDC Gate Driver datasheet (Rev. A) | PDF | HTML | 2025年 4月 30日 |
| * | Radiation & reliability report | DRV8351-SEP Single-Event Effects (SEE) Report | PDF | HTML | 2025年 1月 22日 |
| * | Radiation & reliability report | DRV8351-SEP Production Flow and Reliability Report | PDF | HTML | 2025年 1月 21日 |
| * | Radiation & reliability report | DRV8351-SEP Total Ionizing Dose (TID) Report | PDF | HTML | 2024年 12月 12日 |
設計與開發
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DRV8351EVM — DRV8351 評估模組
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TSSOP (PW) | 20 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點