DP83TG721S-Q1
- IEEE802.3bp 1000BASE-T1 compliant
- OA TC10 compliant, <20µA sleep current
- Local and remote wake up and wake forwarding
- Advanced TSN
- IEEE 1588v2/802.1AS Time Synchronization
- Hardware time-stamping with integrated phase correction
- Highly accurate 1pps signal (±15ns)
- Audio Clocking
- AVB IEEE 1722 media clock generation capability
- Phase synchronized wall clock output: 1KHz to 50MHz
- I2S & TDM8 SCLK/FSYNC/MCLK clock generation
- Open Alliance TC12 Interoperability and EMC compliant
- OA EMC compliant
- SAE J2962-3 EMC Compliant
- Integrated LPF on MDI pins
- MAC Interfaces: MII, RMII, RGMII, and SGMII
- Supported I/O voltages: 3.3V, 2.5V, and 1.8V
- Pin compatible with TI’s 100BASE-T1 PHYs and 1000BASE-T1 PHYs
- Single board design for 100BASE-T1 and 1000BASE-T1 with required BOM change
- Diagnostic tool kit
- Temperature, Voltage, ESD monitor
- Data throughput calculator : Inbuilt MAC packet generator, counter and error checker
- Signal Quality Indicator
- TDR based open and short cable fault detection
- CQI for cable degradation monitoring
- Loopback modes
- AEC-Q100 Qualified
- IEC61000-4-2 ESD : ±8kV contact discharge
The DP83TG721-Q1 is an IEEE 802.3bp and Open Alliance compliant automotive 1000Base-T1 Ethernet physical layer transceiver. The DP83TG721-Q1 provides all physical layer functions needed to transmit and receive data over unshielded/shielded single twisted-pair cables. The device provides xMII flexibility with support for RGMII and SGMII MAC interfaces.
DP83TG721-Q1 supports OA TC10 low power sleep feature (with wake forwarding) to reduce system power consumption when communication is not required. This device offers the Diagnostic Tool Kit, with an extensive list of real-time monitoring tools, debug tools and test modes.
DP83TG721-Q1 integrates IEEE 1588v2/802.1AS hardware time stamping & fractional PLL enabling highly accurate time synchronization. The fractional PLL enables frequency/phase synchronization of the Wall Clock eliminating need for external VCXO and generating wide range of time synchronized frequencies needed for Audio, Video and other ADAS applications.
DP83TG721-Q1 also integrates IEEE 1722 CRF decode to generate Media Clock (wall clock synchronized) for AVB & other Audio standards. The DP83TG721-Q1 is also capable of generating FSYNC/SCLK (wall clock synchronized) for I2S/TDM8 interface needed for audio applications.
The DP83TG721-Q1 is compatible to TI’s 100BASE-T1 PHYs and 1000BASE-T1 PHYs enabling design scalability with single board for both speeds.
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技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | DP83TG721x-Q1 1000BASE-T1 Automotive Ethernet PHY with Advanced TSN and AVB datasheet (Rev. A) | PDF | HTML | 2024/6/10 | ||
| 白皮書 | Time Sensitive Networking With Ethernet PHY | PDF | HTML | 2025/1/14 | |||
| Application brief | Advancing Humanoid Robotics with Single Pair Ethernet | PDF | HTML | 2024/12/13 | |||
| 應用說明 | SGMII Troubleshooting Guide | PDF | HTML | 2024/11/5 | |||
| 應用說明 | Basic Ethernet Interface Debug With Linux | PDF | HTML | 2024/10/11 | |||
| 應用說明 | How to Integrate Linux Driver Into Your System | PDF | HTML | 2024/7/12 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
DP83TG721EVM-MC — DP83TG721 1000Base-T1 至 1000Base-T 媒體轉換器評估模組
DP83TG721-Q1-DESIGN — DP83TG721-Q1 1000BASE-T1 PHY with TC-10 & IEEE 1588v2 / 802.1AS
ETHERNET-SW — 乙太網路 PHY 驅動程式和工具
德州儀器乙太網路實體層 (PHY) 收發器的驅動程式支援透過序列管理介面 (MDC/MDIO) 進行通訊，以配置及讀取 PHY 暫存器。如需 Linux 和 RTOS 驅動程式，請前往我們的 github。
TIDA-020071 — TDA4 四路車用 PHY RGMII 參考設計
此參考設計透過 RGMII 乙太網路擴充連接器介接 Jacinto™ 7 處理器 EVM 板。藉由 TI 汽車乙太網路實體層 (PHY) 新增四個汽車乙太網路。設計採用 TI 的 DP83TC818S-Q1 100Mbps/s 與 DP83TG721S-Q1 1000Mbps 單對乙太網路 (SPE) PHY。使用耦合網路，以 12V 耦合至數據線。
TIDA-020079 — 區域參考設計
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RHA) | 36 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。