DP83630
- IEEE 1588 V1 and V2 Supported
- UDP/IPv4, UDP/IPv6, and Layer2 Ethernet Packets Supported
- IEEE 1588 Clock Synchronization
- Selectable Frequency Synchronized Low Jitter Clock Output
- Timestamp Resolution of 8 ns
- Allows Sub 10 ns Synchronization to Master Reference
- 12 IEEE 1588 GPIOs for Trigger or Capture
- Deterministic, Low Transmit and Receive Latency
- Dynamic Link Quality Monitoring
- TDR Based Cable Diagnostic and Cable Length Detection
- 10/100 Mb/s Packet BIST (Built in Self Test)
- Error-Free Operation up to 150 Meters CAT5 Cable
- ESD Protection - 8 kV Human Body Model
- 2.5 V and 3.3 V I/Os and MAC Interface
- Auto-MDIX for 10/100 Mbps
- Auto-Crossover in Forced Modes of Operation
- RMII Rev. 1.2 and MII MAC Interface
- RMII Master Mode
- 25 MHz MDC and MDIO Serial Management Interface
- IEEE 802.3u 100BASE-FX Fiber Interface
- IEEE 1149.1 JTAG
- Programmable LED Support for Link, 10 /100 Mb/s Mode, Duplex, Activity, and Collision Detect
- Optional 100BASE-TX Fast Link-Loss Detection
- Industrial Temperature Range
- 48 Pin WQFN Package (7mm) x (7mm)
PHYTER is a trademark of Texas Instruments. All trademarks are the property of their respective owners.
The DP83630 Precision PHYTER device delivers the highest level of precision clock synchronization for real time industrial connectivity based on the IEEE 1588 standard. The DP83630 has deterministic, low latency and allows choice of microcontroller with no hardware customization required. The integrated 1588 functionality allows system designers the flexibility and precision of a close to the wire timestamp. The three key 1588 features supported by the device are:
— Packet time stamps for clock synchronization
— Integrated IEEE 1588 synchronized low jitter clock generation
— Synchronized event triggering and time stamping through GPIO
DP83630 offers innovative diagnostic features unique to Texas Instruments, including dynamic monitoring of link quality during standard operation for fault prediction. These advanced features allow the system designer to implement a fault prediction mechanism to detect and warn of deteriorating and changing link conditions. This single port fast Ethernet transceiver can support both copper and fiber media.
技術文件
設計與開發
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SNLC036 — Software Design Guide and C Software Reference Library
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TIDM-HAHSCPTO — 高可用性高速計數器 (HSC) 和脈衝串輸出 (PTO) 參考設計
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| WQFN (RHS) | 48 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。