DAC5672
- 14-Bit Dual Transmit Digital-to-Analog Converter (DAC)
- 275 MSPS Update Rate
- Single-Supply: 3 V to 3.6 V
- High Spurious-Free Dynamic Range (SFDR): 84 dBc at 5 MHz
- High Third-Order Two-Tone Intermodulation (IMD3): 79 dBc at 15.1 MHz and 16.1 MHz
- WCDMA Adjacent Channel Leakage Ratio (ACLR): 78 dB at Baseband
- WCDMA ACLR: 73 dB at 30.72 MHz
- Independent or Single Resistor Gain Control
- Dual or Interleaved Data
- On-Chip 1.2-V Reference
- Low Power: 330 mW
- Power-Down Mode: 9 mW
- Package: 48-Pin Thin-Quad Flat Pack (TQFP)
The DAC5672 device is a monolithic, dual-channel, 14-bit, high-speed DAC with on-chip voltage reference.
Operating with update rates of up to 275 MSPS, the DAC5672 offers exceptional dynamic performance, tight-gain, and offset matching characteristics that make the device well-suited in I/Q baseband or direct IF communication applications.
Each DAC has a high-impedance, differential-current output suitable for single-ended or differential analog-output configurations. External resistors allow scaling the full-scale output current for each DAC separately or together, typically between 2 mA and 20 mA. An accurate on-chip voltage reference is temperature-compensated and delivers a stable 1.2-V reference voltage. Optionally, an external reference may be used.
The DAC5672 has two, 14-bit, parallel input ports with separate clocks and data latches. For flexibility, the DAC5672 supports multiplexed data for each DAC on one port when operating in interleaved mode.
The DAC5672 is specifically designed for a differential transformer-coupled output with a 50-Ω doubly-terminated load. For a 20-mA full-scale output current, a 4:1 impedance ratio (resulting in an output power of 4 dBm) and 1:1 impedance ratio transformer (–2 dBm output power) are supported.
The DAC5672 is available in a 48-pin TQFP package. Pin compatibility between family members provides 12-bit (DAC5662) and 14-bit (DAC5672) resolutions. Furthermore, the DAC5672 is pin compatible to the DAC2904 and AD9767 dual DACs. The device is characterized for operation over the industrial temperature range from –40°C to 85°C.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | Dual 14 Bit 275 MSPS DAC datasheet (Rev. D) | 2017/8/4 | |||
| 使用指南 | TSW6011EVM Quick Start Guide (Rev. D) | 2016/8/17 | ||||
| 應用說明 | Wideband Complementary Current Output DAC Single-Ended Interface (Rev. A) | 2015/5/8 | ||||
| 設計指南 | Direct Down-Conversion System With I/Q Correction (TIDA-00078 CerTIfied Design) | 2013/7/23 | ||||
| 應用說明 | High Speed, Digital-to-Analog Converters Basics (Rev. A) | 2012/10/23 | ||||
| 應用說明 | Passive Terminations for Current Output DACs | 2008/11/10 | ||||
| 應用說明 | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 2008/6/8 | ||||
| 應用說明 | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 2008/6/2 |
設計與開發
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MATCHGAIN-CALC — 寬頻補償電流輸出 DAC 至 SE 介面：改善增益和合規電壓擺幅的匹配
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High-speed digital-to-analog converters (DACs) most often use a (...)
TIDA-00078 — 具有 I/Q 校正的直接降壓轉換系統
在 TSW6011EVM 的現場可編程閘陣列 (FPGA) 中實作的 I/Q 修正區塊可幫助使用者在無線系統中採用直接降頻轉換接收器架構。I/Q 校正區塊包含單分接頭盲算法，可修正複數零 IF 接收器系統中的頻率無關 I/Q 不平衡。除了 I/Q 校正區塊，FPGA 還包括一個數位增益區塊、一個數位功率測量區塊、2 個內插區塊、一個 I/Q 偏移校正區塊和一個正交混合區塊。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TQFP (PFB) | 48 | Ultra Librarian |
訂購與品質
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