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邏輯和電壓轉換
正反器、鎖存器和暫存器
D 型正反器

CY74FCT2574T

現行

具有 3 態輸出和串聯阻尼電阻的八路 D 型暫存器

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CY74FCT2574T

現行
產品規格表 立即訂購

產品詳細資料

Number of channels 8 Technology family FCT Input type TTL, TTL-Compatible CMOS Output type 3-State, CMOS Clock frequency (max) (MHz) 100 IOL (max) (mA) 12 IOH (max) (mA) -15 Supply current (max) (µA) 200 Features Damping resistors, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 8 Technology family FCT Input type TTL, TTL-Compatible CMOS Output type 3-State, CMOS Clock frequency (max) (MHz) 100 IOL (max) (mA) 12 IOH (max) (mA) -15 Supply current (max) (µA) 200 Features Damping resistors, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
SSOP (DBQ) 20 51.9 mm² (8.65 mm × 6 mm) SOIC (DW) 20 131.84 mm² (12.8 mm × 10.3 mm)
  • Function and Pinout Compatible With FCT and F Logic
  • 25- Output Series Resistors to Reduce Transmission-Line Reflection Noise
  • Reduced VOH (Typically = 3.3 V) Version of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • Matched Rise and Fall Times
  • Fully Compatible With TTL Input and Output Logic Levels
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • 3-State Outputs
  • 12-mA Output Sink Current
    15-mA Output Source Current
  • Edge-Triggered D-Type Inputs
  • 250-MHz Typical Switching Rate
  • Function and Pinout Compatible With FCT and F Logic
  • 25- Output Series Resistors to Reduce Transmission-Line Reflection Noise
  • Reduced VOH (Typically = 3.3 V) Version of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • Matched Rise and Fall Times
  • Fully Compatible With TTL Input and Output Logic Levels
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • 3-State Outputs
  • 12-mA Output Sink Current
    15-mA Output Source Current
  • Edge-Triggered D-Type Inputs
  • 250-MHz Typical Switching Rate

The CY74FCT2574T is a high-speed, low-power, octal D-type flip-flop featuring separate D-type inputs for each flip-flop. On-chip termination resistors at the outputs reduce system noise caused by reflections. The CY74FCT2574T can replace the CY74FCT574T to reduce noise in an existing design. This device has 3-state outputs for bus-oriented applications. A buffered clock (CP) and output-enable (OE\) inputs are common to all flip-flops. The CY74FCT2574T is identical to the CY74FCT2374T, except that on the CY74FCT2574T all outputs are on one side of the package and all inputs are on the other side. The flip-flops in the CY74FCT2574T store the state of their individual D inputs that meet the setup-time and hold-time requirements on the low-to-high CP transition. When OE\ is low, the contents of the flip-flops are available at the outputs. When OE\ is high, the outputs are in the high-impedance state. The state of OE\ does not affect the state of the flip-flops.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The CY74FCT2574T is a high-speed, low-power, octal D-type flip-flop featuring separate D-type inputs for each flip-flop. On-chip termination resistors at the outputs reduce system noise caused by reflections. The CY74FCT2574T can replace the CY74FCT574T to reduce noise in an existing design. This device has 3-state outputs for bus-oriented applications. A buffered clock (CP) and output-enable (OE\) inputs are common to all flip-flops. The CY74FCT2574T is identical to the CY74FCT2374T, except that on the CY74FCT2574T all outputs are on one side of the package and all inputs are on the other side. The flip-flops in the CY74FCT2574T store the state of their individual D inputs that meet the setup-time and hold-time requirements on the low-to-high CP transition. When OE\ is low, the contents of the flip-flops are available at the outputs. When OE\ is high, the outputs are in the high-impedance state. The state of OE\ does not affect the state of the flip-flops.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 8-Bit Register datasheet 2001/10/11
* 使用指南 CYFCT Parameter Measurement Information 2001/4/2
應用說明 Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022/12/15

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