CY74FCT2543T
- Function and Pinout Compatible With FCT and F Logic
- 25-
Output Series Resistors to Reduce Transmission-Line Reflection Noise - Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
- Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
- Ioff Supports Partial-Power-Down Mode Operation
- Matched Rise and Fall Times
- Fully Compatible With TTL Input and Output Logic Levels
- 12-mA Output Sink Current
15-mA Output Source Current - Separation Controls for Data Flow in Each Direction
- Back-to-Back Latches for Storage
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
- 3-State Outputs
The CY74FCT2543T octal latched transceiver contains two sets of eight D-type latches. Separate latch enable (LEAB\, LEBA\) and output enable (OEAB\, OEBA\) inputs permit each latch set to have independent control of inputting and outputting in either direction of data flow. For example, for data flow from A to B, the A-to-B enable (CEAB\) input must be low to enter data from A or to take data from B, as indicated in the function table. With CEAB\ low, a low signal on the A-to-B latch enable (LEAB\) input makes the A-to-B latches transparent; a subsequent low-to-high transition of LEAB\ puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB\ and OEAB\ both low, the 3-state B output buffers are active and reflect data present at the output of the A latches. Control of data from B to A is similar, but uses CEAB\, LEAB\, and OEAB\ inputs. On-chip termination resistors at the outputs reduce system noise caused by reflections. The CY74FCT2543T can replace the CY74FCT543T to reduce noise in an existing design.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | 8-Bit Latched Transceiver With 3-State Outputs datasheet (Rev. C) | 2001/11/2 | |||
| * | 使用指南 | CYFCT Parameter Measurement Information | 2001/4/2 |
設計與開發
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14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SSOP (DBQ) | 24 | Ultra Librarian |
| SOIC (DW) | 24 | Ultra Librarian |