CDCUN1208LP
- Supports PCIe Gen1, Gen2, Gen3
- Configuration Options (Through Pins or
SPI/I2C):
- Input Type (HCSL, LVDS, LVCMOS)
- Output Type (HCSL, LVDS, LVCMOS)
- Signal Edge Rate (Slow, Medium, Fast)
- Clock Input Divide Value (/1, /2, /4, /8) – IN2 Only
- Low-Power Consumption and Power Management Features, Including 1.8-V Operation and Output Enable Control
- Integrated Voltage Regulators to Improve PSNR
- Excellent Additive Jitter Performance
- 200 fs RMS (10 kHz to 20 MHz), LVDS at
100 MHz - 160 fs RMS (10 kHz to 20 MHz), HCSL at
100 MHz
- 200 fs RMS (10 kHz to 20 MHz), LVDS at
- Maximum Operating Frequency:
- Differential Mode: up to 400 MHz
- LVCMOS Mode: up to 250 MHz
- ESD Protection Exceeds 2-kV HBM, 500-V CDM
- Industrial Temperature Range (–40°C to 85°C)
- Wide Supply Range (1.8 V, 2.5 V, or 3.3 V)
The CDCUN1208LP is a 2:8 fan-out buffer featuring a wide operating supply range, two universal differential/single-ended inputs, and universal outputs (HCSL, LVDS, or LVCMOS) with edge-rate control. The clock buffer supports PCIe Gen1, Gen2 and Gen3. One of the device inputs includes a divider that provides divide values of /1, /2, /4, or /8. The CDCUN1208LP is offered in a 32-pin QFN package, reducing the solution footprint. The device is flexible and easy to use. The state of certain pins determines device configuration at power up. Alternately, the CDCUN1208LP provides a SPI/I2C port with which a host processor controls device settings. The CDCUN1208LP delivers excellent additive jitter performance, and low power consumption. The output section includes four dedicated supply pins enabling the operation of output ports from different power supply domains. This provides the ability to clock devices switching at different LVCMOS levels without the need for external logic level translation circuitry.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | CDCUN1208LP 400-MHz Low Power 2:8 Fan-Out Buffer With Universal Inputs and Outputs datasheet (Rev. D) | PDF | HTML | 2019/4/18 |
設計與開發
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CDCUN1208LPEVM — CDCUN1208LP 評估模組
The CDCUN1208LP is a 2:8 fan-out buffer featuring a wide operating supply range, two universal differential/ single ended inputs, and universal outputs (HCSL, LVDS, or LVCMOS) with clock edge rate control. One of the device inputs includes a divider that provides divide values of /1, /2, /4, and (...)
SCAC133 — CDCUN1208LP EVM Control GUI
CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體
時鐘樹架構是一款時鐘樹合成工具，可根據您的系統需求產生時鐘樹解決方案，進而簡化您的設計流程。此工具可從廣泛的計時產品資料庫中汲取資料，產生系統級多晶片計時解決方案。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RHB) | 32 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。