CDCS504-Q1

現行

時鐘緩衝器/時鐘倍頻器

立即訂購

產品規格表

document-pdfAcrobat CDCS504-Q1 Clock Buffer and Clock Multiplier datasheet (英文) PDF | HTML

CDCS504-Q1

現行

產品規格表

立即訂購

產品詳細資料

Number of outputs

Output type

LVCMOS

Output frequency (max) (MHz)

108

Core supply voltage (V)

3.3

Output supply voltage (V)

3.3

Input type

LVCMOS

Operating temperature range (°C)

-40 to 105

Features

3.3-V VCC/VDD, Pin programmable

Rating

Automotive

Number of outputs

Output type

LVCMOS

Output frequency (max) (MHz)

108

Core supply voltage (V)

3.3

Output supply voltage (V)

3.3

Input type

LVCMOS

Operating temperature range (°C)

-40 to 105

Features

3.3-V VCC/VDD, Pin programmable

Rating

Automotive

TSSOP (PW)

19.2 mm² (3 mm × 6.4 mm)

Qualified for Automotive Applications
AEC-Q100 Test Guidance With the Following Results:
- Device Temperature Grade 2: –40°C to 105°C Ambient Operating Temperature Range
- Device HBM ESD Classification Level H2
- Device CDM ESD Classification Level C3B
Part of a Family of Easy-to-Use Clock Generator Devices
Clock Multiplier With Selectable Output Frequency
Frequency Multiplication Selectable Between x1 or x4 With One External Control Pin
Output Disable Through Control Pin
Single 3.3-V Device Power Supply
Wide Temperature Range: –40°C to 105°C
Low Space Consumption 8-Pin TSSOP Package
Create a Custom Design Using the CDCS504-Q1 With the WEBENCH^® Power Designer

Qualified for Automotive Applications
AEC-Q100 Test Guidance With the Following Results:
- Device Temperature Grade 2: –40°C to 105°C Ambient Operating Temperature Range
- Device HBM ESD Classification Level H2
- Device CDM ESD Classification Level C3B
Part of a Family of Easy-to-Use Clock Generator Devices
Clock Multiplier With Selectable Output Frequency
Frequency Multiplication Selectable Between x1 or x4 With One External Control Pin
Output Disable Through Control Pin
Single 3.3-V Device Power Supply
Wide Temperature Range: –40°C to 105°C
Low Space Consumption 8-Pin TSSOP Package
Create a Custom Design Using the CDCS504-Q1 With the WEBENCH^® Power Designer

The CDCS504-Q1 device is a LVCMOS input clock buffer with selectable frequency multiplication.

The CDCS504-Q1 has an output enable pin.

The device accepts a 3.3-V LVCMOS signal at the input.

The input signal is processed by a phased-locked loop (PLL), whose output frequency is either equal to the input frequency or multiplied by the factor of four.

By this, the device can generate output frequencies between 2 MHz and 108 MHz.

A separate control pin can be used to enable or disable the output. The CDCS504-Q1 device operates in a 3.3-V environment.

It is characterized for operation from –40°C to 105°C and is available in an 8-pin TSSOP package.

The CDCS504-Q1 device is a LVCMOS input clock buffer with selectable frequency multiplication.

The CDCS504-Q1 has an output enable pin.

The device accepts a 3.3-V LVCMOS signal at the input.

The input signal is processed by a phased-locked loop (PLL), whose output frequency is either equal to the input frequency or multiplied by the factor of four.

By this, the device can generate output frequencies between 2 MHz and 108 MHz.

A separate control pin can be used to enable or disable the output. The CDCS504-Q1 device operates in a 3.3-V environment.

It is characterized for operation from –40°C to 105°C and is available in an 8-pin TSSOP package.

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