CD74HCT164
- Buffered inputs
- Asynchronous reset
- Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25°C
- Fanout (overtemperature range)
- Standard Outputs: 10 LSTTL loads
- Bus driver outputs: 15 LSTTL loads
- Wide operating temp range: – 55°C to 125°C
- Balanced propagation delay and transition times
- Significant power reduction compared to LSTTL logic ICs
- HC types
- 2V to 6V operation
- High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
- HCT types
- 4.5V to 5.5V operation
- Direct LSTTL input logic compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
- CMOS input compatibility, II ≤ 1µA at VOL, VOH
The ’HC164 and ’HCT164 are 8-bit, serial-in, parallel-out, shift registers with asynchronous reset. Data is shifted on the positive edge of Clock (CLK). A LOW on the RESET (CLR) pin resets the shift register and all outputs go to the LOW state regardless of the input conditions. Two Serial Data inputs (A and B) are provided, either one can be used as a data enable control.
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| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | CDx4HC164, CDx4HCT164 High-Speed CMOS Logic 8-Bit Serial-In, Parallel-Out Shift Register datasheet (Rev. E) | PDF | HTML | 2024/5/7 | ||
| 應用說明 | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 2022/12/15 |
設計與開發
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開發板
14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOIC (D) | 14 | Ultra Librarian |
| PDIP (N) | 14 | Ultra Librarian |