CD74HC273
- Common clock and asynchronous controller reset
- Positive edge triggering
- Buffered inputs
- Fanout (over temperature range)
- Standard outputs: 10 LSTTL loads
- Bus driver outputs: 15 LSTTL loads
- Wide operating temperature range: –55℃ to 125℃
- Balanced propagation delay and transition times
- Significant power reduction compared to LSTTL Logic ICs
- HC types:
- 2V to 6V operation
- High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
- HCT types:
- 4.5V to 5.5V operation
- Direct LSTTL input logic compatibility, VIL = 0.8V (maximum), VIH = 2V (minimum)
- CMOS input compatibility, II ≤ 1µA at VOL,VOH
The CD54HC273, CD74HC273, CD54HCT273, and CD74HCT273 high speed octal D-Type flip-flops with a direct clear input are manufactured with silicongate CMOS technology. The devices possess the low power consumption of standard CMOS integrated circuits.
Information at the D input transfers to the Q outputs on the positive-going edge of the clock pulse. All eight flip-flops are controlled by a common clock (CLK) and a common reset (/CLR). Resetting is accomplished by a low voltage level independent of the clock. All eight Q outputs reset to a logic 0.
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技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | CDx4HC(T)273 High-Speed CMOS Logic Octal D-Type Flip-Flop with Reset datasheet (Rev. D) | PDF | HTML | 2025/10/28 | ||
| 應用說明 | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 2022/12/15 |
設計與開發
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14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOIC (DW) | 20 | Ultra Librarian |
| PDIP (N) | 20 | Ultra Librarian |