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CD4086B

現行

CMOS 可擴充 4 寬 2 輸入 AND-OR-INVERT 閘

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產品規格表

CD4086B

現行
產品規格表 立即訂購

產品詳細資料

Technology family CD4000 Number of channels 1 Inputs per channel 2 IOL (max) (mA) 6.8 IOH (max) (mA) -6.8 Input type Standard CMOS Output type Push-Pull Features Standard speed (tpd > 50ns) Data rate (max) (Mbps) 8 Rating Catalog Operating temperature range (°C) -55 to 125
Technology family CD4000 Number of channels 1 Inputs per channel 2 IOL (max) (mA) 6.8 IOH (max) (mA) -6.8 Input type Standard CMOS Output type Push-Pull Features Standard speed (tpd > 50ns) Data rate (max) (Mbps) 8 Rating Catalog Operating temperature range (°C) -55 to 125
SOIC (D) 14 51.9 mm² (8.65 mm × 6 mm) PDIP (N) 14 181.42 mm² (19.3 mm × 9.4 mm)
  • Medium-speed operation - tPHL = 90 ns; tPLH = 140 ns (typ.) at 10 V
  • INHIBIT and ENABLE inputs
  • Buffered outputs
  • 100% tested for quiescent current at 20 V
  • Maximum input leakage current of 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (over full package temperature range):
        1 V at VDD = 5 V
        2 V at VDD = 10 V
        2.5 V at VDD = 15 V
  • Standardized, symmetrical output characteristics
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
  • Medium-speed operation - tPHL = 90 ns; tPLH = 140 ns (typ.) at 10 V
  • INHIBIT and ENABLE inputs
  • Buffered outputs
  • 100% tested for quiescent current at 20 V
  • Maximum input leakage current of 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (over full package temperature range):
        1 V at VDD = 5 V
        2 V at VDD = 10 V
        2.5 V at VDD = 15 V
  • Standardized, symmetrical output characteristics
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"

CD4086B contains one 4-wide 2-input AND-OR-INVERT gate with an INHIBIT/(EXP\) input and an ENABLE/EXP input. For a 4-wide A-O-I function INHIBIT/(EXP\) is tied to VSS and ENABLE/EXP to VDD. See Fig. 10 and its associated explanation for applications where a capability greater than 4-wide is required.

The CD4086B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4086B contains one 4-wide 2-input AND-OR-INVERT gate with an INHIBIT/(EXP\) input and an ENABLE/EXP input. For a 4-wide A-O-I function INHIBIT/(EXP\) is tied to VSS and ENABLE/EXP to VDD. See Fig. 10 and its associated explanation for applications where a capability greater than 4-wide is required.

The CD4086B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).
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* 資料表 CD4086B TYPES datasheet (Rev. C) 2003/8/21

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