CD4050B
- CD4049UB inverting
- CD4050B noninverting
- High sink current for driving 2 TTL loads
- High-to-low level logic conversion
- 100% tested for quiescent current at 20V
- Maximum input current of 1µA at 18V over full package temperature range; 100nA at 18V and 25°C
- 5V, 10V, and 15V parametric ratings
The CD4049UB and CD4050B devices are inverting and noninverting hex buffers, and feature logic-level conversion using only one supply voltage (VCC). The input-signal high level (VIH) can exceed the VCC supply voltage when these devices are used for logic-level conversions. These devices are intended for use as CMOS to DTL or TTL converters and can drive directly two DTL or TTL loads. VCC = 5V, VOL ≤ 0.4V, and IOL ≥ 3.3mA.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | CD4049UB and CD4050B CMOS Hex Inverting Buffer and Converter datasheet (Rev. L) | PDF | HTML | 2026/2/4 | ||
| 應用說明 | Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics | 2001/12/3 |
設計與開發
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14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOP (NS) | 16 | Ultra Librarian |
| TSSOP (PW) | 16 | Ultra Librarian |
| PDIP (N) | 16 | Ultra Librarian |
| SOIC (D) | 16 | Ultra Librarian |
| SOIC (DW) | 16 | Ultra Librarian |