AFE7799
- Quad transmitters based on direct up-conversion architecture:
- Up to 600 MHz of RF transmitted bandwidth per chain
- Quad receivers based on 0-IF down-conversion architecture:
- Up to 200 MHz of RF received bandwidth per chain
- Feedback chain based on RF sampling ADC:
- Up to 600 MHz of RF received bandwidth
- RF frequency range: 600 MHz to 6 GHz
- Wideband fractional-N PLL, VCO for TX and RX LO
- Dedicated integer-N PLL, VCO for data converters clock generation
- JESD204B and JESD204C SerDes interface support:
- 8 SerDes transceivers up to 29.5 Gbps
- 8b/10b and 64b/66b encoding
- 16-bit, 12-bit, 24-bit and 32-bit formatting
- Subclass 1 multi-device synchronization
- Package: 17-mm x 17-mm BGA, 0.8-mm pitch
The AFE7799 is a high-performance, multichannel transceiver, integrating four direct up-conversion transmitter chains, four direct down-conversion receiver chains, and two wideband RF sampling digitizing auxiliary chains (feedback paths). The high dynamic range of the transmitter and receiver chains allows generating and receiving 2G, 3G, 4G, and 5G signals for wireless base stations. The low power dissipation and large channels integration makes the AFE7799 suitable to address the power and size constrained 4G and 5G massive MIMO base stations. The wideband and high dynamic range feedback path can assist the digital pre-distortion (DPD) of the power amplifiers in the transmitter chain. The fast SerDes speed can help reducing the number of lanes required to transfer the data in and out.
Each receiver chain of the AFE7799 includes a 28-dB range digital step attenuator (DSA), followed by a wideband passive IQ demodulator, and a baseband amplifier with integrated programmable antialiasing low pass filters, driving a continuous-time sigma-delta ADC. The RX chain can receive an instantaneous bandwidth (IBW) up to 200 MHz. Each receiver channel has two analog peak power detectors and various digital power detectors to assist an external or internal autonomous AGC control for receiver channels, and a RF overload detector for device reliability protection. The integrated QMC (quadrature mismatch compensation) algorithm is capable to continuously monitor and correct for the rx chain I and Q imbalance mismatch without the need to inject any specific signals or perform offline calibration.
Each transmitter chain includes two 14-bit, 3-Gsps IQ DACs, followed by a programmable reconstruction and DAC image rejection filter, an IQ modulator driving a wideband RF amplifier with 39-dB range gain control. The TX chain integrated QMC and LO leakage cancellation algorithms, leveraging the FB path can constantly track and correct for the TX chain IQ mismatch and LO leakage.
The FB path is based on RF sampling architecture, and includes an input RF DSA driving a 14-bit, 3-Gsps RF ADC. The direct sampling architecture provides an inherently wideband receiver chain and simplifies the calibration of the TX chains impairments. Each FB path integrates two independent NCO that allows a fast switching between two observed RF input bands.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | AFE7799 Quad-Channel RF Transceiver With Feedback Path datasheet | PDF | HTML | 2019年 6月 6日 |
| User guide | Interfacing AFE7769DEVM With the Hitek Agilex eSOM7 FPGA | PDF | HTML | 2023年 9月 28日 | |
| Application note | Using AFE77xx in a Digital Pre-distortion System (Rev. B) | 2021年 9月 2日 | ||
| Application note | System Design Considerations when Upgrading from JESD204B to JESD204C (Rev. A) | 2021年 4月 5日 | ||
| Application note | Time Division Duplexing (TDD) in AFE77xx Integrated Transceiver (Rev. A) | 2021年 4月 5日 | ||
| Application note | AFE76xx, AFE77xx, and AFE79xx JESD204 Layer Testing | 2020年 4月 15日 | ||
| User guide | AFE77xx Latte GUI | 2019年 7月 25日 | ||
| Application note | Temp Profile to Maintain Optimum FIT Performance | 2019年 7月 23日 | ||
| Application note | Controlling Latte GUI from Python | 2019年 7月 8日 | ||
| Application note | AFE77xx Power Solutions | 2019年 6月 25日 |
設計與開發
如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。
AFE7769-3P5EVM — 具有 3.5-GHz 支援的 AFE7769 四通道射頻收發器評估模組
AFE7769-3P5 評估模組 (EVM) 是用於評估整合式 RF 收發器 AFE77xx 系列的電路板。AFE7769 和 AFE7799 裝置支援高達四個傳輸、四個接收和二個回饋通道 (4T4R2F),並整合鎖相迴路 (PLL)、用於產生資料轉換器時脈的電壓控制振盪器 (VCO) 及 LO,具有可從 600MHz 調整至 6GHz 的 LO 頻率。
AFE7769-3P5EVM 整合射頻 (RF) 平衡不平衡轉換器和專門支援 3.3GHz 至 3.8GHz 的比對,但可延伸至最高支援 6GHz。AFE77xx 裝置整合八個 JESD204B/C 相容的串聯器/解串器 (SerDes) (...)
AFE7769EVM — AFE7769 四通道射頻收發器評估模組
AFE7769 評估模組 (EVM) 是用於評估整合式 RF 收發器 AFE77xx 系列的電路板。AFE77xx 裝置支援高達四個傳輸、四個接收和二 個回饋通道 (4T4R2F),並整合鎖相迴路 (PLL)、用於產生資料轉換器時脈的電壓控制振盪器 (VCO) 及 LO,具有可從 600MHz 調整至 6GHz 的 LO 頻率。
此標準 EVM 整合 RF 平衡不平衡轉換器,專門支援 600MHz 至 2700MHz。AFE77xx 裝置整合八個 JESD204B/C 相容的串聯器/解串器 (SerDes) 收發器 (最高可達 29.5Gbps),以透過板載 FMC (...)
HTK-3P-AGILEX-ESOM7 — HITEK Agilex eSOM7 with FMC+ connector to RF transceiver EVMs
The Hitek Systems eSOM7 interfaces with the AFE8092, AFE8030, AFE7952, and AFE7920 through an FPGA mezzanine card (FMC) connector. It provides a quick evaluation and prototyping platform for 5G wireless solutions based on Intel’s latest high-performance 10-nm Agilex F-Series FPGA.
TI204C-IP — Request for JESD204 rapid design IP
The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
支援產品和硬體
產品
高速 DAC (>10 MSPS)
高速 ADC (≥10 MSPS)
RF 收發器
RF 發射器
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| FCBGA (ABJ) | 400 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點