產品詳細資料

Resolution (Bits) 24 Sample rate (max) (ksps) 0.24 Number of input channels 8 Interface type SPI Architecture Delta-Sigma Input type Differential, Pseudo-Differential, Single-ended Multichannel configuration Multiplexed Rating Catalog Reference mode External Input voltage range (max) (V) 5.5 Input voltage range (min) (V) 0 Features Buffer, Oscillator, PGA Operating temperature range (°C) -40 to 125 Power consumption (typ) (mW) 8800 Analog supply voltage (min) (V) 2.85 Analog supply voltage (max) (V) 5.5 Digital supply (min) (V) 1.65 Digital supply (max) (V) 5.5
Resolution (Bits) 24 Sample rate (max) (ksps) 0.24 Number of input channels 8 Interface type SPI Architecture Delta-Sigma Input type Differential, Pseudo-Differential, Single-ended Multichannel configuration Multiplexed Rating Catalog Reference mode External Input voltage range (max) (V) 5.5 Input voltage range (min) (V) 0 Features Buffer, Oscillator, PGA Operating temperature range (°C) -40 to 125 Power consumption (typ) (mW) 8800 Analog supply voltage (min) (V) 2.85 Analog supply voltage (max) (V) 5.5 Digital supply (min) (V) 1.65 Digital supply (max) (V) 5.5
SSOP (DB) 28 79.56 mm² (10.2 mm × 7.8 mm)
  • Up to 26.0 bits of effective resolution
  • Low noise PGA with gain 1 to 128
  • Programmable data rate 2.5SPS to 320kSPS
  • Input buffer range includes ground
  • High Performance
    • Nonlinearity: 0.5ppm FSR (typical)
    • Offset drift: 10nV/°C (gain = 128, typical)
    • Gain drift: 0.5ppm/°C FSR (typical)
    • Noise: 11nVRMS (5SPS, gain = 128, typical)
  • 320kSPS, 160kSPS, 80kSPS speed modes
  • Autozero mode reduces offset error
  • Available in 2mm x 2mm QFN package
  • Input multiplexer with open-sensor detection
  • One-shot conversions with single-cycle settling
  • 35µs conversion time for fast channel scanning
  • Internal, external or crystal clock options
  • General purpose input/output pins
  • Offset and gain calibration
  • Analog power supply range: 2.85V to 5.5V
  • Digital power supply range: 1.65V to 5.5V
  • Fully specified from –40°C to +125°C
  • Up to 26.0 bits of effective resolution
  • Low noise PGA with gain 1 to 128
  • Programmable data rate 2.5SPS to 320kSPS
  • Input buffer range includes ground
  • High Performance
    • Nonlinearity: 0.5ppm FSR (typical)
    • Offset drift: 10nV/°C (gain = 128, typical)
    • Gain drift: 0.5ppm/°C FSR (typical)
    • Noise: 11nVRMS (5SPS, gain = 128, typical)
  • 320kSPS, 160kSPS, 80kSPS speed modes
  • Autozero mode reduces offset error
  • Available in 2mm x 2mm QFN package
  • Input multiplexer with open-sensor detection
  • One-shot conversions with single-cycle settling
  • 35µs conversion time for fast channel scanning
  • Internal, external or crystal clock options
  • General purpose input/output pins
  • Offset and gain calibration
  • Analog power supply range: 2.85V to 5.5V
  • Digital power supply range: 1.65V to 5.5V
  • Fully specified from –40°C to +125°C

The ADS125R11, ADS125R13 and ADS125R14 are high resolution, 24-bit, delta-sigma (ΔΣ), analog-to-digital converters with data rates up to 320kSPS with three, six and nine channels. The ADS125R11 and ADS125R14 are pin-to-pin performance upgrades to the ADS1255 and ADS1256 ADCs.

The ADS125R1x devices provide low offset and gain drift with low INL error. Autozero operation tracks offset error over time and temperature. Three speed modes optimize power consumption, sample rate, bandwidth and resolution for the application.

The ADCs are comprised of an input buffer, PGA, a delta-sigma modulator and a low latency digital filter. The flexible input multiplexer accepts single-ended and differential signals with integrated current sources for open-sensor detection. The input buffer reduces measurement error caused by signal loading of the sensor. The PGA provides gains up to x128 to increase measurement resolution.

The digital filter provides sample rates from 2.5SPS (for high resolution) to 320kSPS (for high throughput and high bandwidth applications). In the 320kSPS mode, eight channels of data are measured in less than 300µs with 16.9 bits effective resolution. The sinc3 filter provides greater than 100dB rejection of 50Hz and 60Hz interference signals.

The SPI-compatible interface supports 2-, 3- or 4-wire communication modes. The SPI CRC helps to verify error-free transmission of data. The register map CRC verifies register settings against unexpected changes. The general-purpose, input-input digital pins offer an output signal for error detection, and a clock output to synchronize other ADCs in multiple channel systems.

The ADS125R11, ADS125R13 and ADS125R14 are high resolution, 24-bit, delta-sigma (ΔΣ), analog-to-digital converters with data rates up to 320kSPS with three, six and nine channels. The ADS125R11 and ADS125R14 are pin-to-pin performance upgrades to the ADS1255 and ADS1256 ADCs.

The ADS125R1x devices provide low offset and gain drift with low INL error. Autozero operation tracks offset error over time and temperature. Three speed modes optimize power consumption, sample rate, bandwidth and resolution for the application.

The ADCs are comprised of an input buffer, PGA, a delta-sigma modulator and a low latency digital filter. The flexible input multiplexer accepts single-ended and differential signals with integrated current sources for open-sensor detection. The input buffer reduces measurement error caused by signal loading of the sensor. The PGA provides gains up to x128 to increase measurement resolution.

The digital filter provides sample rates from 2.5SPS (for high resolution) to 320kSPS (for high throughput and high bandwidth applications). In the 320kSPS mode, eight channels of data are measured in less than 300µs with 16.9 bits effective resolution. The sinc3 filter provides greater than 100dB rejection of 50Hz and 60Hz interference signals.

The SPI-compatible interface supports 2-, 3- or 4-wire communication modes. The SPI CRC helps to verify error-free transmission of data. The register map CRC verifies register settings against unexpected changes. The general-purpose, input-input digital pins offer an output signal for error detection, and a clock output to synchronize other ADCs in multiple channel systems.

下載 觀看有字幕稿的影片 影片

技術文件

找不到結果。請清除您的搜尋條件,然後再試一次。
檢視所有 1
重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 ADS125R1x 3, 6 and 9-Channel, 320kSPS, 24-Bit, ΔΣ ADCs With Input Buffer and PGA datasheet PDF | HTML 2026/10/16

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

ADS125R14EVM-PDK — ADS125R14 評估模組

The ADS125R14 evaluation module (EVM) is a platform for evaluating the performance of the ADS125R14, which is a 24-bit, 8-channel, 320kSPS, multiplexed delta-sigma (ΔΣ) analog-to-digital converter (ADC) designed for low-latency, high precision data acquisition systems. The ADS125R14 (...)

使用指南: PDF | HTML
支援產品和硬體
有庫存
限制:
??asset.out-of-stock-ti_zh_TW??
無法提供
計算工具

ANALOG-ENGINEER-CALC — PC software analog engineer's calculator

類比工程師的計算機旨在加速類比電路設計工程師定期使用的許多重複計算。此基於 PC 的工具提供圖形介面,列出各種常見計算,從使用回饋電阻器設定運算放大器增益到選擇適當的電路設計元件以穩定類比數位轉換器 (ADC) 驅動緩衝電路。

除了作為獨立工具使用外,此計算機還與類比工程師口袋參考中描述的概念相得益彰。

支援產品和硬體
封裝 針腳 CAD 符號、佔位空間與 3D 模型
SSOP (DB) 28 Ultra Librarian

訂購與品質

建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

內容係由 TI 和社群貢獻者依「現狀」提供,且不構成 TI 規範。檢視使用條款。

若有關於品質、封裝或訂購 TI 產品的問題,請參閱 TI 支援。​​​​​​​​​​​​​​

影片