ADC3421
- Quad Channel
- 12-Bit Resolution
- Single Supply: 1.8 V
- Serial LVDS Interface
- Flexible Input Clock Buffer with Divide-by-1, -2, -4
- SNR = 70.2 dBFS, SFDR = 87 dBc at
fIN = 70 MHz - Ultra-Low Power Consumption:
- 98 mW/Ch at 125 MSPS
- Channel Isolation: 105 dB
- Internal Dither and Chopper
- Support for Multi-Chip Synchronization
- Pin-to-Pin Compatible with 14-Bit Version
- Package: VQFN-56 (8 mm × 8 mm)
The ADC342x are a high-linearity, ultra-low power, quad-channel, 12-bit, 25-MSPS to 125-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC342x family supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 12-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | ADC342x Quad-Channel, 12-Bit, 25-MSPS to 125-MSPS, Analog-to-Digital Converter datasheet (Rev. A) | PDF | HTML | 2015/9/30 |
設計與開發
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TIDA-00499 — 使用差動放大器和 HS ADC 的暫態及數位故障記錄器 AFE 參考設計
數位故障記錄器 (DFR) 可在 60/50 Hz 下偵測 17/20 μs 的暫態，而暫態記錄器則可擷取能在毫秒內達到峰值與衰退的干擾。此參考設計展示以 1 MHz 擷取 DFR 暫態輸入，針對暫態構造器則以 25 MHz 擷取暫態輸入。正負暫態 (<=100-kV 峰值) 皆可視應用需求以不同解析度擷取 (12 位元至 14 位元解析度)，並使用驅動高速轉換器的差動放大器在 2 準確度內執行擷取。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RTQ) | 56 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。