ADC12QJ1600-SP
- Radiation
Performance:
- Total Ionizing Dose (TID): 300 krad (Si)
- Single Event Latchup (SEL): 120 MeV-cm2/mg
- Single Event Upset (SEU) immune registers
- ADC Core:
- Resolution: 12 Bit
- Maximum sampling rate: 1.6GSPS
- Non-interleaved architecture
- Internal dither reduces high-order harmonics
- Performance specifications (–1dBFS):
- SNR (100 MHz): 57.4dBFS
- ENOB (100 MHz): 9.1 Bits
- SFDR (100 MHz): 64dBc
- Noise floor (–20dBFS): –147dBFS
- Full-scale input voltage: 800mVPP-DIFF
- Full-power input bandwidth: 6GHz
- JESD204C Serial data interface:
- Support for 2 to 8 total SerDes lanes
- Maximum baud-rate: 17.16Gbps
- 64B/66B and 8B/10B encoding modes
- Subclass-1 support for deterministic latency
- Compatible with JESD204B receivers
- Optional internal sampling clock generation
- Internal PLL and VCO (7.2–8.2GHz)
- SYSREF Windowing eases synchronization
- Four clock outputs simplify system clocking
- Reference clocks for FPGA or adjacent ADC
- Reference clock for SerDes transceivers
- Timestamp input and output for pulsed systems
- Power consumption (1 GSPS): 1.9W
- Power supplies: 1.1V, 1.9V
ADC12QJ1600-SP is a quad channel, 12-bit, 1.6GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the device suited for a variety of multi-channel communications systems.
Full-power input bandwidth (-3dB) of 6GHz enables direct RF sampling of L-band and S-band.
A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.
JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.
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技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | ADC12QJ1600-SP Quad Channel 1.6GSPS, 12-Bit, Analog-to-Digital Converter (ADC) with JESD204C Interface datasheet (Rev. B) | PDF | HTML | 2025/2/19 | ||
| * | 輻射及可靠性報告 | ADC12QJ1600-SHP Production Flow and Reliability Report | 2025/3/10 | |||
| Application brief | DLA Approved Optimizations for QML Products (Rev. C) | PDF | HTML | 2025/6/17 | |||
| 技術文章 | How SHP in plastic packaging addresses 3 key space application design challenges | PDF | HTML | 2022/10/17 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
ADC12QJ1600EVM — 具有 JESD204C 介面且適用於四通道、12 位元、1.6GSPS ADC 的 ADC12QJ1600 評估模組
TSW12QJ1600EVM — ADC12QJ1600-Q1 8 通道（兩個同步 4 通道）12 位元 1.6GSPS JESD204C 介面 ADC 評估模組
ADC09xJ800, ADC09xJ1300, ADC12xJ800 and ADC12xJ1600 IBIS-AMI Model (Rev. A)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| FCCSP (ALR) | 144 | Ultra Librarian |