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數據轉換器
類比轉數位轉換器 (ADC)
高速 ADC (≥10 MSPS)

ADC12QJ1600-SEP

現行

Radiation-tolerant, 30krad, 12-bit quad 1.6GSPS ADC with JESD204C interface

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產品規格表

ADC12QJ1600-SEP

現行
產品規格表 立即訂購

產品詳細資料

Sample rate (max) (Msps) 1600 Resolution (Bits) 12 Number of input channels 4 Interface type JESD204B, JESD204C Analog input BW (MHz) 6000 Features Ultra High Speed Rating Space Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 1910 Architecture Folding Interpolating SNR (dB) 57.4 ENOB (Bits) 9 SFDR (dB) 64 Operating temperature range (°C) -55 to 125 Input buffer Yes Radiation, TID (typ) (krad) 30 Radiation, SEL (MeV·cm2/mg) 43
Sample rate (max) (Msps) 1600 Resolution (Bits) 12 Number of input channels 4 Interface type JESD204B, JESD204C Analog input BW (MHz) 6000 Features Ultra High Speed Rating Space Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 1910 Architecture Folding Interpolating SNR (dB) 57.4 ENOB (Bits) 9 SFDR (dB) 64 Operating temperature range (°C) -55 to 125 Input buffer Yes Radiation, TID (typ) (krad) 30 Radiation, SEL (MeV·cm2/mg) 43
FCCSP (ALR) 144 100 mm² (10 mm × 10 mm)
  • Radiation Tolerance:
    • Total Ionizing Dose (TID): 30krad (Si)
    • Single Event Latchup (SEL): 43 MeV-cm2/mg
    • Single Event Upset (SEU) immune registers
  • Space-enhanced plastic (space EP):
    • Meets ASTM E595 outgassing specification
    • Vendor item drawing (VID) V62/22610
    • Temperature range: –55°C to 125°C
    • One fabrication, assembly, and test site
    • Wafer lot traceability
    • Extended product life cycle
    • Extended product change notification
  • ADC Core:
    • Resolution: 12 Bit
    • Maximum sampling rate: 1.6GSPS
    • Non-interleaved architecture
    • Internal dither reduces high-order harmonics
  • Performance specifications (–1dBFS):
    • SNR (100 MHz): 57.4dBFS
    • ENOB (100 MHz): 9.1 Bits
    • SFDR (100 MHz): 64dBc
    • Noise floor (–20 BFS): –147dBFS
  • Full-scale input voltage: 800mVPP-DIFF
  • Full-power input bandwidth: 6GHz
  • JESD204C Serial data interface:
    • Support for 2 to 8 total SerDes lanes
    • Maximum baud-rate: 17.16Gbps
    • 64B/66B and 8B/10B encoding modes
    • Subclass-1 support for deterministic latency
    • Compatible with JESD204B receivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO (7.2 – 8.2GHz)
  • SYSREF Windowing eases synchronization
  • Four clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (1GSPS): 1.9W
  • Power supplies: 1.1V, 1.9V
  • Radiation Tolerance:
    • Total Ionizing Dose (TID): 30krad (Si)
    • Single Event Latchup (SEL): 43 MeV-cm2/mg
    • Single Event Upset (SEU) immune registers
  • Space-enhanced plastic (space EP):
    • Meets ASTM E595 outgassing specification
    • Vendor item drawing (VID) V62/22610
    • Temperature range: –55°C to 125°C
    • One fabrication, assembly, and test site
    • Wafer lot traceability
    • Extended product life cycle
    • Extended product change notification
  • ADC Core:
    • Resolution: 12 Bit
    • Maximum sampling rate: 1.6GSPS
    • Non-interleaved architecture
    • Internal dither reduces high-order harmonics
  • Performance specifications (–1dBFS):
    • SNR (100 MHz): 57.4dBFS
    • ENOB (100 MHz): 9.1 Bits
    • SFDR (100 MHz): 64dBc
    • Noise floor (–20 BFS): –147dBFS
  • Full-scale input voltage: 800mVPP-DIFF
  • Full-power input bandwidth: 6GHz
  • JESD204C Serial data interface:
    • Support for 2 to 8 total SerDes lanes
    • Maximum baud-rate: 17.16Gbps
    • 64B/66B and 8B/10B encoding modes
    • Subclass-1 support for deterministic latency
    • Compatible with JESD204B receivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO (7.2 – 8.2GHz)
  • SYSREF Windowing eases synchronization
  • Four clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (1GSPS): 1.9W
  • Power supplies: 1.1V, 1.9V

ADC12QJ1600-SEP is a quad channel, 12-bit, 1.6GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the device suited for a variety of mulch-chanel communications systems.

Full-power input bandwidth (-3 dB) of 6 GHz enables direct RF sampling of L-band and S-band.

A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.

JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.

ADC12QJ1600-SEP is a quad channel, 12-bit, 1.6GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the device suited for a variety of mulch-chanel communications systems.

Full-power input bandwidth (-3 dB) of 6 GHz enables direct RF sampling of L-band and S-band.

A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.

JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.
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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 ADC12QJ1600-SEP Quad Channel 1.6-GSPS, 12-Bit, Analog-to-Digital Converter (ADC) with JESD204C Interface datasheet (Rev. A) PDF | HTML 2025/2/24
* 輻射及可靠性報告 ADC12QJ1600-SEP Production Flow and Reliability Report (Rev. A) PDF | HTML 2025/3/12

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開發板

ADC12QJ1600EVM — 具有 JESD204C 介面且適用於四通道、12 位元、1.6GSPS ADC 的 ADC12QJ1600 評估模組

ADC12QJ1600 評估模組 (EVM) 專為評估 ADC12QJ1600-Q1 系列高速類比轉數位轉換器 (ADC) 所設計。本 EVM 搭載 ADC12QJ1600-Q1 晶片，該晶片為具備 JESD204B 介面的 12 位元、四通道 1.6GSPS ADC，可評估 12 位元系列中所有取樣率之單通道、雙通道及四通道車用或工業級裝置。
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模擬型號

ADC09xJ800, ADC09xJ1300, ADC12xJ800 and ADC12xJ1600 IBIS-AMI Model (Rev. A)

SBAM512A.ZIP (22293 KB) - IBIS-AMI 模型
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FCCSP (ALR) 144 Ultra Librarian
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