74AC11138
- Designed specifically for high-speed memory decoders and data transmission systems
- Incorporates three enable inputs to simplify cascading and/or data reception
- Center-Pin VCC and GND configurations minimize high-speed switching noise
- EPIC ™ (Enhanced-Performance Implanted CMOS) 1-µm process
- 500-mA typical latch-up immunity at 125 °C
- Package options include plastic small-outline (D) and thin shrink small-outline (PW) packages, and standard plastic 300-mil DIPs (N)
The 74AC11138 circuit is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times.
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| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | 74AC11138 3-Line to 8-Line Decoder/Demultiplexer datasheet (Rev. C) | PDF | HTML | 2024/5/22 |