UCC27511A
- Input Pins Capable of Withstanding –5V Below GND pin
- Low-Cost Gate-Driver Device Offering Superior Replacement of NPN and PNP Discrete Solutions
- Strong Sink Current Offers Enhanced Immunity Against Miller Turnon
- Split Output Configuration (Allows Easy and Independent Adjustment of Turnon and Turnoff Speeds)
- Fast Propagation Delays (13ns typical)
- Fast Rise and Fall Times (8ns and 7ns typical)
- 4.5V to 18V Single Supply Range
- Outputs Held Low During VDD UVLO (Ensures Glitch-Free Operation at Power Up and Power Down)
- TTL and CMOS Compatible Input-Logic Threshold (Independent of Supply Voltage)
- Wide Hysteresis (1V typical) for High-Noise Immunity
- Dual-Input Design (Choice of an Inverting (IN– Pin) or Non-Inverting (IN+ Pin) Driver Configuration)
- Unused Input Pin can be Used for Enable or Disable Function
- Output Held Low when Input Pins are Floating
- Input Pin Absolute Maximum Voltage Levels Not Restricted by VDD Pin Bias Supply Voltage
The UCC27511A device is a compact gate driver that offers superior replacement of NPN and PNP discrete driver (buffer circuit) solutions. The UCC27511A device is a single-channel low-side, high-speed gate driver rated for MOSFETs, IGBTs, and emerging wide-bandgap power devices such as GaN. The device features fast rise times, fall times, and propagation delays, making the UCC27511A device suitable for high-speed applications. Its asymmetrical 4A peak source and 8A peak sink currents boost immunity against parasitic Miller turnon effect. The split output configuration enables easy and independent adjustment of rise and fall times using only two resistors and eliminating the need for an external diode. Features including wide input hysteresis and negative input voltage handling enhance transient immunity.
기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 |
|---|---|---|---|---|---|
| * | 데이터 시트 | UCC27511A Single-Channel High-Speed Low-Side Gate Driver With 4A Peak Source and 8A Peak Sink datasheet (Rev. A) | PDF | HTML | 2024. 1. 17 | |
| 애플리케이션 노트 | Review of Different Power Factor Correction (PFC) Topologies' Gate Driver Needs | PDF | HTML | 2024. 1. 22 | ||
| 애플리케이션 노트 | Using a Single-Output Gate-Driver for High-Side or Low-Side Drive (Rev. B) | PDF | HTML | 2023. 9. 8 | ||
| 애플리케이션 노트 | Benefits of a Compact, Powerful, and Robust Low-Side Gate Driver | PDF | HTML | 2021. 11. 10 | ||
| Application brief | External Gate Resistor Selection Guide (Rev. A) | 2020. 2. 28 | |||
| Application brief | Understanding Peak IOH and IOL Currents (Rev. A) | 2020. 2. 28 | |||
| Application brief | How to overcome negative voltage transients on low-side gate drivers' inputs | 2019. 1. 18 | |||
| Application brief | Enable Function with Unused Differential Input | 2018. 7. 11 | |||
| Application brief | Low-Side Gate Drivers With UVLO Versus BJT Totem-Pole | 2018. 3. 16 |
설계 및 개발
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| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| SOT-23 (DBV) | 6 | Ultra Librarian |
주문 및 품질
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.